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Pooja_03's avatar
Pooja_03
Icon for New Contributor rankNew Contributor
1 year ago

MAX10 (10M50DAF484C8G): Maximum Frequency for CLK In, CLK Out, and GPIO Pins"

Hello, I am working with the MAX10 FPGA (part number: 10M50DAF484C8G) and would like to know the maximum frequency that can be used for the following: CLK In CLK Out Normal GPIO pins Could yo...
Hdl
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi,


You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.


Just so you know, actual achievable frequency depends on design and system-specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.


Link for IBIS Model:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html


Regards,

Aqid