New Contributor
Frequent ContributorHi Eric,
Are you want the design which have the IP setting as below requirements:
Besides that, can you do a block diagram for top module so that I can have a better understanding about your design?
To get more information about the ethernet IP, you may refer to the link below https://www.rocketboards.org/foswiki/Main/WebHome
Besides that, you can visit our FPGA design store webpage which got a lot example design that you can refer to https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html
Best regards,
zying
New ContributorHi Zying,
I would like to have a self-contained 10/100/1000 ethernet controller with MAC and also be able to send and receive UART data all on its own without CPU intervention. I want to mimic what the CH9121 device does but place all of this logic inside the FPGA and then be able to communicate to the NIOS V processor through RX/TX lines of this "ethernet controller". I am not that familiar with the inner workings of ethernet communication yet so I have a bit to learn but looking for some guidance on how to implement something like this. I may be able to draw a block diagram of how I think it might work but may take a couple of days. I'm getting back into the FPGA design again and I am a bit rusty with all of this. Any help is greatly appreciated.
Thanks,
Eric Norton
