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Altera_Forum's avatar
Altera_Forum
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14 years ago

MatLab 2009/11 Quartus 9.1/11.1sp2

Hi,

I have a Cyclone IV E FPGA.

I am working on a Project using Quartus 11.1sp2 and MatLab 2010.

But I also need some older projects which were programmed on Quartus 9.1 and MatLab 2009.

Sadly the Modell on Simulink arent compatible.

Now I have installed both, but now I cant compile any Project either on MatLab 2009 or on MatLab 2010.

I get an error message on MatLab 2010 :

Error (23031): Evaluation of Tcl script

and on MatLab 2009 I cant even choose the right Board in the signal compiler.

Hope somebody can help me.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Your terms are confusing. I think when you say MATLAB, you mean DSP Builder. The MATLAB version should not cause any issues except that older versions are not supported by newer versions of DSP Builder. (R2009b of MATLAB is supported by Quartus 11.1sp2).

    Can you load your old DSP Builder design into a newer DSP Builder? What exactly happens when you try to compile using the signal compiler? (Signal compiler doesn't list boards, so do you mean device families?)
  • Altera_Forum's avatar
    Altera_Forum
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    Hi,

    yeah u r right, when Im talking about MatLab I mean the DSP Builder of the same Version like Quartus, which is installed for the specific MatLab Version.

    And I am using MatLab 2009a not b, which makes it so difficult :wacko:

    when I load the DSP Builder Design from 2009a in 2010a I get an error:

    ERROR: Can't open revision: STEP_LED_R2R (project: STEP_LED_R2R). The revision is not compatible with the installed version of the Quartus II software. Opening the revision will overwrite the old revision database. If you wish to overwrite the old revision database, make sure to specify the -force option.

    while executing

    "project_open -revision $projectname $projectname"

    invoked from within

    "if ([project_exists $projectname]) {

    project_open -revision $projectname $projectname

    } else {

    project_new -revision $projectname $projectname

    }"

    (file "C:\DOKUME~1\ADMINI~1\LOKALE~1\Temp\generateProject3703794844369760641.tcl" line 19)

    ------------------------------------------------

    Error (23031): Evaluation of Tcl script C:\DOKUME~1\ADMINI~1\LOKALE~1\Temp\generateProject3703794844369760641.tcl unsuccessful

    Error: Quartus II 32-bit Shell was unsuccessful. 1 error, 0 warnings

    Error: Peak virtual memory: 109 megabytes

    Error: Processing ended: Tue Mar 13 16:35:09 2012

    Error: Elapsed time: 00:00:19

    Error: Total CPU time (on all processors): 00:00:09

    Same Error occures, when I want to build it in MatLab 2009a and when I build a new DSP Builder Design in 2010a, which definitly works earlier.

    One think also confuse me. While compiling it in 2009a I get the INFO message in the DSP BUILDER SIGNAL COMPILER:

    Info: Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Full Version

    Instead of using Version 9.1!

    All the problems ocurred after installing Version 9.1!
  • Altera_Forum's avatar
    Altera_Forum
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    MATLAB R2009a will almost certainly work with DSP Builder 11.1SP2. It's just that the installer won't detect older versions. You can get around this by entering the path to MATLAB manually on the MATLAB selection page.

    Try loading the quartus project manually in Quartus II 11.1SP2 first and then resave it. This should allow DSP Builder to use it.

    It's possible your MATLAB installation has references to two different Quartus/DSP Builder versions. To check this, run the following commands:

    path
    javaclasspath

    and check that there are only paths from one version.
  • Altera_Forum's avatar
    Altera_Forum
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    in both versions of MatLab there is only one Version of DSP Builder added and its the right one. But my Javaclasspath DYNAMIC is empty, is it bad?

    How can I load a MatLab/Simulink Modell load in Quartus?

    Quartus needs .qpf and to get this I need to compile the Simulink modell with the DSP BUILDER Signal Compiler and that wont work.
  • Altera_Forum's avatar
    Altera_Forum
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    Depends if the static class path contains a reference to DSP Builder.

    If the static class path doesn't point to a DSP Builder jar file then the signal compiler window wouldn't even appear.

    The error message you're getting when using the Signal compiler seems to imply that you already have a qpf in the same directory as your mdl file. (It may be in the directory called <model>_dspbuilder).
  • Altera_Forum's avatar
    Altera_Forum
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    Yes, after deleting the directory, and compiling again it works on MatLab 2010.

    In MatLab 2009a after compiling the .mdl with Signal Compiler (Device EP3... instead of EP4...) I want to compile it in a HiL-Block and get an error

    Info: Running Quartus II 32-bit Analysis & Synthesis

    Info: Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Full Version

    Info: Processing started: Wed Mar 14 13:18:10 2012

    Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk_test -c clk_test_HIL

    Info (20029): Only one processor detected - disabling parallel compilation

    Info (12021): Found 2 design units, including 2 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/clk_test.mdl

    Info (12023): Found entity 1: clk_test

    Info (12023): Found entity 2: clk_test_Interface

    Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/ckdiv.v is missing

    Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/cnt.v is missing

    Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/LEDmeter.v is missing

    Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/SEG7_LUT.v is missing

    Info (12021): Found 6 design units, including 6 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/ckdiv.v

    Info (12023): Found entity 1: ckdiv_25m_dc50

    Info (12023): Found entity 2: ckdiv_50m_dc50

    Info (12023): Found entity 3: ckdiv_pfrq_dc50

    Info (12023): Found entity 4: ckdiv_ifrq_dc50

    Info (12023): Found entity 5: ckdiv_ifrq_pw1

    Info (12023): Found entity 6: ckdiv_50m_dc50_cnt

    Info (12021): Found 1 design units, including 1 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/cnt.v

    Info (12023): Found entity 1: cnt16r

    Info (12021): Found 5 design units, including 5 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/ledmeter.v

    Info (12023): Found entity 1: LedMeterLin8

    Info (12023): Found entity 2: LedMeterLin16

    Info (12023): Found entity 3: LedMeterLog8

    Info (12023): Found entity 4: LedMeterLog16

    Info (12023): Found entity 5: LedMeterLog18

    Info (12021): Found 2 design units, including 2 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/seg7_lut.v

    Info (12023): Found entity 1: SEG7_LUT

    Info (12023): Found entity 2: SEG7_LUT_EXTENDED

    Info (12021): Found 1 design units, including 1 entities, in source file /altera/11.1/quartus/dsp_builder/lib/hilaltr_node.v

    Info (12023): Found entity 1: hilaltr_node

    Warning (10275): Verilog HDL Module Instantiation warning at clk_test_HIL.v(117): ignored dangling comma in List of Port Connections

    Info (12021): Found 1 design units, including 1 entities, in source file clk_test_hil.v

    Info (12023): Found entity 1: clk_test_HIL

    Info (12127): Elaborating entity "clk_test_HIL" for the top level hierarchy

    Error (10130): Verilog HDL error at clk_test_HIL.v(38): parameter "N_NODE_IR_BITS" is not a formal parameter of instantiated module File: C:/01_Bachelorarbeit_Romanowski/02_MatLab/94_CHM_fxpt_mmvr/fxpt_mmvr/clk_test_dspbuilder/clk_test_HIL.v Line: 38

    Error (12153): Can't elaborate top-level user hierarchy
  • Altera_Forum's avatar
    Altera_Forum
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    This looks like you're mixing the generated output of one version of DSP Builder with another.

    hilaltr_node.v changed in DSP Builder 11.0 to not have a parameter called N_NODE_IR_BITS. (At least I think that's what happened - I'm not very expert at Verilog).

    One possibility is that you have an environment variable called QUARTUS_ROOTDIR that's pointing at your 11.1 quartus. I'm really not sure why you're continuing to use your old version of Quartus/DSP Builder.

    My advice is to clear out everything but your source files (mdl file + dependent HDL files for HDL Import if you're using it). Then stick to the new version of DSP Builder. It's very hard to give help for such an old version.
  • Altera_Forum's avatar
    Altera_Forum
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    The only reason why I try to use Quartus 9.1 is, because I need some DSP Builder Designs, which were generated with MatLab/Simulink 2009a.

    And I read that they arent compatible to each other. And when I tried it, I get an Error, that the Design was made in an older Version and it wont work.

    Maybe u can help me, that I can use it also in MatLab 2010a with Quartus 11.1.
  • Altera_Forum's avatar
    Altera_Forum
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    If you read back through my posts I explained that you could use MATLAB R2009a with DSP Builder 11.1 and I explained how you could do it.

    --- Quote Start ---

    MATLAB R2009a will almost certainly work with DSP Builder 11.1SP2. It's just that the installer won't detect older versions. You can get around this by entering the path to MATLAB manually on the MATLAB selection page.

    --- Quote End ---

    All your previous errors were down to you having files generated by older versions of DSP Builder lying around. If you delete all these files and use the newer version of DSP Builder/Quartus exclusively you shouldn't have these problems.