Honored Contributor
Honored ContributorYes, after deleting the directory, and compiling again it works on MatLab 2010.
In MatLab 2009a after compiling the .mdl with Signal Compiler (Device EP3... instead of EP4...) I want to compile it in a HiL-Block and get an error Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Full Version Info: Processing started: Wed Mar 14 13:18:10 2012 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk_test -c clk_test_HIL Info (20029): Only one processor detected - disabling parallel compilation Info (12021): Found 2 design units, including 2 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/clk_test.mdl Info (12023): Found entity 1: clk_test Info (12023): Found entity 2: clk_test_Interface Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/ckdiv.v is missing Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/cnt.v is missing Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/LEDmeter.v is missing Warning (12019): Can't analyze file -- file ../../../../../Dokumente und Einstellungen/chm/eigene dateien/Studienarbeit/matlab/fxpt_mmvr/SEG7_LUT.v is missing Info (12021): Found 6 design units, including 6 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/ckdiv.v Info (12023): Found entity 1: ckdiv_25m_dc50 Info (12023): Found entity 2: ckdiv_50m_dc50 Info (12023): Found entity 3: ckdiv_pfrq_dc50 Info (12023): Found entity 4: ckdiv_ifrq_dc50 Info (12023): Found entity 5: ckdiv_ifrq_pw1 Info (12023): Found entity 6: ckdiv_50m_dc50_cnt Info (12021): Found 1 design units, including 1 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/cnt.v Info (12023): Found entity 1: cnt16r Info (12021): Found 5 design units, including 5 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/ledmeter.v Info (12023): Found entity 1: LedMeterLin8 Info (12023): Found entity 2: LedMeterLin16 Info (12023): Found entity 3: LedMeterLog8 Info (12023): Found entity 4: LedMeterLog16 Info (12023): Found entity 5: LedMeterLog18 Info (12021): Found 2 design units, including 2 entities, in source file /01_bachelorarbeit_romanowski/02_matlab/94_chm_fxpt_mmvr/fxpt_mmvr/seg7_lut.v Info (12023): Found entity 1: SEG7_LUT Info (12023): Found entity 2: SEG7_LUT_EXTENDED Info (12021): Found 1 design units, including 1 entities, in source file /altera/11.1/quartus/dsp_builder/lib/hilaltr_node.v Info (12023): Found entity 1: hilaltr_node Warning (10275): Verilog HDL Module Instantiation warning at clk_test_HIL.v(117): ignored dangling comma in List of Port Connections Info (12021): Found 1 design units, including 1 entities, in source file clk_test_hil.v Info (12023): Found entity 1: clk_test_HIL Info (12127): Elaborating entity "clk_test_HIL" for the top level hierarchy Error (10130): Verilog HDL error at clk_test_HIL.v(38): parameter "N_NODE_IR_BITS" is not a formal parameter of instantiated module File: C:/01_Bachelorarbeit_Romanowski/02_MatLab/94_CHM_fxpt_mmvr/fxpt_mmvr/clk_test_dspbuilder/clk_test_HIL.v Line: 38 Error (12153): Can't elaborate top-level user hierarchy
