Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThis looks like you're mixing the generated output of one version of DSP Builder with another.
hilaltr_node.v changed in DSP Builder 11.0 to not have a parameter called N_NODE_IR_BITS. (At least I think that's what happened - I'm not very expert at Verilog). One possibility is that you have an environment variable called QUARTUS_ROOTDIR that's pointing at your 11.1 quartus. I'm really not sure why you're continuing to use your old version of Quartus/DSP Builder. My advice is to clear out everything but your source files (mdl file + dependent HDL files for HDL Import if you're using it). Then stick to the new version of DSP Builder. It's very hard to give help for such an old version.