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ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

make PLL code above the nios_core when I click on "Generate HDL"

Hi,

I add PLL in nios_core.

when I generate HDL, the PLL code is generated in nios_core.

My question is:

I would like to make PLL code above the nios_core when I click on "Generate HDL" in Platform Designer. is there a way to do that?

when I export c1 of PLL in Platform Designer, the connection among c1 and other components are broken automatically. That is to say only one of the connection and c1 export port could be remained in Platform Designer.

The purpose that I would like to export c1 is that I would like to make c1 as the input clock of other components that are in the same level as nios_core.

Platform

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    9 months ago

    Many ways to do this. You could put the PLL in your design outside of the system and use a clock bridge to bring it in. You could "push down" all components in your system into a subsystem and use a clock bridge to send the clock to them as well as export the clock outside the system. Or you could just leave the PLL where it is and use a clock bridge.

    It's up to you how you want to organize things, but a clock bridge component is the key.

  • ZhiqiangLiang's avatar
    ZhiqiangLiang
    Icon for Occasional Contributor rankOccasional Contributor
    9 months ago

    @sstrell

    Thank you!

    You told me 3 ways, but I have no idea about how to implement them.

    in this link, https://www.intel.com/content/www/us/en/docs/programmable/683609/22-1/clock-bridge.html, The crystal oscillator is connected to the clock bridge in FPGA. My idea is to use PLL to take place of the clock bridge, furthermore, the PLL verilog code should be added manually rather than be generated inside NIOS core by Platform Designer.

    in the above link, the clock bridge just like a PLL, is my understanding correct?

    my question is:

    how to add PLL Verilog code in Quartus to connect to crystal oscillator from PCB? the outputs of PLL will be fed into the NIOS core and other components. My question might be how to manually instantiate IP in Quartus but not in Platform Designer.

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      9 months ago

      Your link just goes to the PD user guide, so it's not clear what you are referring to here.

      It seems like you are asking that if you have a crystal on your board, you want to use it as the reference clock directly into a PLL in Platform Designer. Yes, you can. Export the refclk input to the PLL from the system and assign it to an input clock pin in the Pin Planner, assuming you are setting your PD system as your top-level for your Quartus project. If you are instantiating the PD system at a lower level, you'll need to make sure your port mappings are correct to connect from the input clock pin to the exported input refclk of the PLL.

      But then you are asking about having the PLL outside of PD. In that case, like I said, you'll need to instantiate the PLL in an HDL file and then instantiate the PD system, connecting the clock output of the PLL to the exported input of a clock bridge component, which in turn distributes the clock to all components in the system. If you don't use a clock bridge, you would need to export the clock inputs of every component in the system and connect them in your HDL to the PLL clock output instead of simply clicking dots in PD.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    9 months ago

    Hi,


    Is there any further concern on the suggestions provided?


    Thanks,

    Regards,

    Sheng