make PLL code above the nios_core when I click on "Generate HDL"

Many ways to do this. You could put the PLL in your design outside of the system and use a clock bridge to bring it in. You could "push down" all components in your system into a subsystem and use a clock bridge to send the clock to them as well as export the clock outside the system. Or you could just leave the PLL where it is and use a clock bridge.

It's up to you how you want to organize things, but a clock bridge component is the key.