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Altera_Forum's avatar
Altera_Forum
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17 years ago

LVDS ADC to DDR ram

I am trying to take data from an 8 channel ADC that happens to have an LVDS output. I used the ALTLVDS function to make this data into a readable memory mapped interface. I am not sure that is exactly what I want. I have data flying out of this ADC at 10MHz x 8 channels and I want to directly store it to DDR memory since the data I am going to collect is around 1MB. I was thinking of using a streaming interface and the SGDMDA, but I don't know how to convert a memory mapped output to streaming, or if that is even possible. Do I have to write my own VHDL? There must be a million people that want to do this same exact thing. Does anyone have some examples I could reference?

Thanks,

Andrew

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What you need to do is write a bit of HDL code to create a custom SOPC component. This component should read the data from the ADC, probably put it in a FIFO, and then output it as an Avalon stream source. Then in SOPC builder connect your component to the SGDMA stream input, and it should be able to write the data to memory.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Sounds easy! I have been struggling with this. I created a custom block that outputs the data in a streaming format. I have 8 ADC channels @ 12 bits a piece. So, my custom block zero pads the 12bits so each channel is 16bits. Then, I output my data as a Avalon-ST with 16bits per symbol and 8 symbols per beat. I made a signal called valid and just made it 1 all the time. Not sure if this is ok or not, and I made a ready, which is just an input that does nothing. Again, I am not sure this is correct, what should I do. So, now the SGDMA is expecting my symbols to be 8 bits....whats up with that? Also, I need to change my symbols into packets? Why? I don't know. Any help on this whole setup would be greatly appreciated.

    Thanks,

    Andrew
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You'll need a FIFO between your component and the SGDMA. I think the easier would be to use a dual clock FIFO, with its input in the clock domain of your ADC, and the output in the domain of the SGDMA (which should be higher than the one of the ADC). You can find a dual clock Avalon Stream FIFO in SOPC builder that you can use for that.

    If you have a new valid data on each clock cycle, you can indeed make the 'valid' signal 1 all the time. But if I were you I would add a way to turn the stream off (by connecting this valid signal to a pio, as an example) and have the software enable the transfer only once the DMA is properly configured.

    You should be able to set up the SGDMA to 16bits/8 symbols per beat too, or use a stream bridge to convert it to a more traditional size, such as 8bits/4 symbols per beat.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hey there,

    Thanks for the advice on the PIO to control valid. Good suggestion! I do have a FIFO in my system. Another question, do I need a timing adapter somewhere in my setup? Can I somehow use 16bits/symbol on my custom block output or do I need to change it to 8bits per symbol (even though in reality it is a 16bit word that I need)? Here is an outline of what I have in SOPC:

    AD_LVDS - ALTLVDS megafunction (just added it into SOPC builder, no changes to it)

    AD_Zero_Pad_Data_Converter - my custom function. Here is where I am confused. My data is really 16bit data 8 symbols per beat. Seems like all the other stuff after wants 8 bits per symbol. Is this ok? Code is at the bottom.

    Dual Clock Fifo (16 bits per symbol 8 symbols per beat)

    Data format adapter(can't find a way to convert this to 8 bits per symbol)

    ST bytes to Packets ( expects: Data width = 8 bits; Bits per symbol = 8.

    not sure why the hell I need to make everything packets, I guess SGDMA expects this)

    Data format adapter

    SGDMA

    Thanks for any advice/help,

    Andrew

    Here is my code:

    ENTITY AD_Zero_Pad_Data_Converter IS

    PORT

    (

    rx_in : IN STD_LOGIC_VECTOR (95 DOWNTO 0);

    clock : IN STD_LOGIC := '0';

    ready : IN STD_LOGIC;

    ADC_Data_Ready : IN STD_LOGIC :='0';

    valid : OUT STD_LOGIC;

    rx_out : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)

    );

    END AD_Zero_Pad_Data_Converter;

    ARCHITECTURE SYN OF AD_Zero_Pad_Data_Converter IS

    signal rx_outCh1 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh2 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh3 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh4 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh5 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh6 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh7 : STD_LOGIC_VECTOR(15 downto 0);

    signal rx_outCh8 : STD_LOGIC_VECTOR(15 downto 0);

    BEGIN

    rx_outCh1 <= "0000" & rx_in(11 DOWNTO 0);

    rx_outCh2 <= "0000" & rx_in(23 DOWNTO 12);

    rx_outCh3 <= "0000" & rx_in(35 DOWNTO 24);

    rx_outCh4 <= "0000" & rx_in(47 DOWNTO 36);

    rx_outCh5 <= "0000" & rx_in(59 DOWNTO 48);

    rx_outCh6 <= "0000" & rx_in(71 DOWNTO 60);

    rx_outCh7 <= "0000" & rx_in(83 DOWNTO 72);

    rx_outCh8 <= "0000" & rx_in(95 DOWNTO 84);

    valid <= ADC_Data_Ready;

    END SYN;
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You can declare 8 bits per symbols and double the number of symbols per beat in your input, it won't change anything (except if you use packets). So just declare 8 bits per symbol and 16 sywbols per beat, and SOPC builder will be happy.

    You only need packets support if you want the DMA to start and stop retreiving the data at specific times. In your case you have continuous data so you should disable it. I think there is an option in the SGDMA to enable/disable packet support.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    HI

    I am working on very much the same stuff u were working on using Altera DE3 board with Strartix III FPGA. But i am using my own verilog code for capturing LVDS data from the HSTC Ports and deserializing the 8 data channels. me n my partner also have a nios application designed which can communicate with a PC via USB link. for now it is just reading stuff from onchip memory and sending it to PC.

    Coming to the problem, now the target is to send the deserilized data of 8 channels to PC using NIOS USB application. We started from an example to get this NIOS USB thing working. Much of the stuff on SOPC was already done. i have never worked with Verilog-NIOS interface before. I have created a SOPC part for my verilog code with an streaming output. tried using dual clock FIFO with SCDMA to connect it to memory interface but cant get rid of SOPC errors. the auto insert adapters get rids of some errors but creates new ones. my whole project is stuck because i cant get this interface working. just need to write this streaming output to memory. any help from u guys will be really appriciated.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    K, Finally got rid of all the errors but i m not sure if i have connected the blocks properly, specially the SGDMA controller. An image of SOPC Builder System contents is attached. My coustom block is ADC_0. if some1 can check it 4 me, i would be greatful.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    the descriptor read and write masters need to be connected to a RAM where you'll have the descriptors. The descriptors hold the configuration and results of the DMA transfers (address, length, status...). You can connect them to a small dedicated on-chip RAM (that also needs to be connected to the CPU) or to the main RAM.

    I'm surprised by the number of adapters you had to insert... Couldn't you generate a stream output directly compatible with the dc-fifo and sgdma?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for replying.

    I cant use external RAM as all of my IO banks are already used. I will use small onchip RAM but how small it should be?

    About adapters.. i tried to avoid them but the problem is that the output of my ADC is not packetized. I can disable/enable packeting for FIFO but couldnt find this option for SGDMA. so had to insert "bytes to packet converter" and all the adapters are to get this converter interfaced properly. i tried but couldnt find a way around it.

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    A descriptor is only 32 bytes, so a small on-chip memory (1k) is more than enough. If you are short on resources and want to use all the memory blocks in your main on-chip ram you can also put your descriptors there. Just connect the descriptor reader and writer master interfaces to the on-chip RAM you already have.

    I think that if you set up a number of bytes to read in the descriptor, the SGDMA will ignore the start/stop signals. Then you can add those signals on your ADC stream output and put them to always 0. I agree that there should be a way to completely remove them from the SGDMA input though.