LVDS ADC to DDR ram

You'll need a FIFO between your component and the SGDMA. I think the easier would be to use a dual clock FIFO, with its input in the clock domain of your ADC, and the output in the domain of the SGDMA (which should be higher than the one of the ADC). You can find a dual clock Avalon Stream FIFO in SOPC builder that you can use for that.

If you have a new valid data on each clock cycle, you can indeed make the 'valid' signal 1 all the time. But if I were you I would add a way to turn the stream off (by connecting this valid signal to a pio, as an example) and have the software enable the transfer only once the DMA is properly configured.

You should be able to set up the SGDMA to 16bits/8 symbols per beat too, or use a stream bridge to convert it to a more traditional size, such as 8bits/4 symbols per beat.