LVDS ADC to DDR ram

HI

I am working on very much the same stuff u were working on using Altera DE3 board with Strartix III FPGA. But i am using my own verilog code for capturing LVDS data from the HSTC Ports and deserializing the 8 data channels. me n my partner also have a nios application designed which can communicate with a PC via USB link. for now it is just reading stuff from onchip memory and sending it to PC.

Coming to the problem, now the target is to send the deserilized data of 8 channels to PC using NIOS USB application. We started from an example to get this NIOS USB thing working. Much of the stuff on SOPC was already done. i have never worked with Verilog-NIOS interface before. I have created a SOPC part for my verilog code with an streaming output. tried using dual clock FIFO with SCDMA to connect it to memory interface but cant get rid of SOPC errors. the auto insert adapters get rids of some errors but creates new ones. my whole project is stuck because i cant get this interface working. just need to write this streaming output to memory. any help from u guys will be really appriciated.