I am trying to take data from an 8 channel ADC that happens to have an LVDS output. I used the ALTLVDS function to make this data into a readable memory mapped interface. I am not sure that is exactly what I want. I have data flying out of this ADC at 10MHz x 8 channels and I want to directly store it to DDR memory since the data I am going to collect is around 1MB. I was thinking of using a streaming interface and the SGDMDA, but I don't know how to convert a memory mapped output to streaming, or if that is even possible. Do I have to write my own VHDL? There must be a million people that want to do this same exact thing. Does anyone have some examples I could reference? Thanks, Andrew

What you need to do is write a bit of HDL code to create a custom SOPC component. This component should read the data from the ADC, probably put it in a FIFO, and then output it as an Avalon stream source. Then in SOPC builder connect your component to the SGDMA stream input, and it should be able to write the data to memory.

Sounds easy! I have been struggling with this. I created a custom block that outputs the data in a streaming format. I have 8 ADC channels @ 12 bits a piece. So, my custom block zero pads the 12bits so each channel is 16bits. Then, I output my data as a Avalon-ST with 16bits per symbol and 8 symbols per beat. I made a signal called valid and just made it 1 all the time. Not sure if this is ok or not, and I made a ready, which is just an input that does nothing. Again, I am not sure this is correct, what should I do. So, now the SGDMA is expecting my symbols to be 8 bits....whats up with that? Also, I need to change my symbols into packets? Why? I don't know. Any help on this whole setup would be greatly appreciated. Thanks, Andrew

You'll need a FIFO between your component and the SGDMA. I think the easier would be to use a dual clock FIFO, with its input in the clock domain of your ADC, and the output in the domain of the SGDMA (which should be higher than the one of the ADC). You can find a dual clock Avalon Stream FIFO in SOPC builder that you can use for that. If you have a new valid data on each clock cycle, you can indeed make the 'valid' signal 1 all the time. But if I were you I would add a way to turn the stream off (by connecting this valid signal to a pio, as an example) and have the software enable the transfer only once the DMA is properly configured. You should be able to set up the SGDMA to 16bits/8 symbols per beat too, or use a stream bridge to convert it to a more traditional size, such as 8bits/4 symbols per beat.

Hey there, Thanks for the advice on the PIO to control valid. Good suggestion! I do have a FIFO in my system. Another question, do I need a timing adapter somewhere in my setup? Can I somehow use 16bits/symbol on my custom block output or do I need to change it to 8bits per symbol (even though in reality it is a 16bit word that I need)? Here is an outline of what I have in SOPC: AD_LVDS - ALTLVDS megafunction (just added it into SOPC builder, no changes to it) AD_Zero_Pad_Data_Converter - my custom function. Here is where I am confused. My data is really 16bit data 8 symbols per beat. Seems like all the other stuff after wants 8 bits per symbol. Is this ok? Code is at the bottom. Dual Clock Fifo (16 bits per symbol 8 symbols per beat) Data format adapter(can't find a way to convert this to 8 bits per symbol) ST bytes to Packets ( expects: Data width = 8 bits; Bits per symbol = 8. not sure why the hell I need to make everything packets, I guess SGDMA expects this) Data format adapter SGDMA Thanks for any advice/help, Andrew Here is my code: ENTITY AD_Zero_Pad_Data_Converter IS PORT ( rx_in : IN STD_LOGIC_VECTOR (95 DOWNTO 0); clock : IN STD_LOGIC := '0'; ready : IN STD_LOGIC; ADC_Data_Ready : IN STD_LOGIC :='0'; valid : OUT STD_LOGIC; rx_out : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) ); END AD_Zero_Pad_Data_Converter; ARCHITECTURE SYN OF AD_Zero_Pad_Data_Converter IS signal rx_outCh1 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh2 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh3 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh4 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh5 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh6 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh7 : STD_LOGIC_VECTOR(15 downto 0); signal rx_outCh8 : STD_LOGIC_VECTOR(15 downto 0); BEGIN rx_outCh1 <= "0000" & rx_in(11 DOWNTO 0); rx_outCh2 <= "0000" & rx_in(23 DOWNTO 12); rx_outCh3 <= "0000" & rx_in(35 DOWNTO 24); rx_outCh4 <= "0000" & rx_in(47 DOWNTO 36); rx_outCh5 <= "0000" & rx_in(59 DOWNTO 48); rx_outCh6 <= "0000" & rx_in(71 DOWNTO 60); rx_outCh7 <= "0000" & rx_in(83 DOWNTO 72); rx_outCh8 <= "0000" & rx_in(95 DOWNTO 84); valid <= ADC_Data_Ready; END SYN;

You can declare 8 bits per symbols and double the number of symbols per beat in your input, it won't change anything (except if you use packets). So just declare 8 bits per symbol and 16 sywbols per beat, and SOPC builder will be happy. You only need packets support if you want the DMA to start and stop retreiving the data at specific times. In your case you have continuous data so you should disable it. I think there is an option in the SGDMA to enable/disable packet support.

LVDS ADC to DDR ram | Altera Community

16 Replies

Altera_Forum
Honored Contributor
16 years ago
This is what i have done as i understood. I have connected the Descriptor read/write to Descript_mem as well as the onchip_mem (main ram). m_write is connected only to the onchip_mem. I have also attached a JPEG image. if u can check once more, i will be greatful.

Regards
Altera_Forum
Honored Contributor
16 years ago
You don't have to connect the descriptor masters to both memories, you just need to connect them to your descriptor memory.
You don't need to connect the CPU instruction master to the descriptor memory, the data master is enough. That memory will not contain any executable code for the CPU.

When you write the software, don't forget to put the descriptor structures in the correct memory! If you use static allocation or malloc calls, they will end up in the main RAM instead.
Altera_Forum
Honored Contributor
16 years ago
Thanx a lot.

I got it now. will be troubling u again very soon :P

Thanx again.
Altera_Forum
Honored Contributor
16 years ago
Hey omaranwar,

I have had some luck with this whole process. Still working through a few bugs and funny things that happen, but I can give you some guidance. One thing we figured out that was important is to use the Dual Clock Ram with Back pressure. There are two types of dual clock ram, use the one that is just called on chip ram, and check the box for dual clock. You can send me a private message and I can help u out a bit.

-Andrew
Altera_Forum
Honored Contributor
16 years ago
Hey Andrew,

I have sent you a private message, can you please respond.

Omar
Altera_Forum
Honored Contributor
16 years ago
Hi
I am stuck on ALTLVDS Megafunction. I am tring to pass a HSTC Pin input (which is the clock from ADC connected at HSTC true LVDS pin) to the ALTLVDS as a reference to internal PLL of the megafunction. it genrates this error in fitter.
"Error: Can't place Left/Right or Top/Bottom PLL "LVDS:ins3|altlvds_rx:altlvds_rx_component|LVDS_lvds_rx:auto_generated|pll" -- I/O pin HSTCC_RX_p[0] (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device"

What i have found out so far is that I need a dedicated pins for the reference of PLL. How do transfer the data coming from a TRUE LVDS pin to a dedicated pin? or is there some other way to bypass this?

Regards
Omar

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LVDS ADC to DDR ram

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