LVDS ADC to DDR ram

Sounds easy! I have been struggling with this. I created a custom block that outputs the data in a streaming format. I have 8 ADC channels @ 12 bits a piece. So, my custom block zero pads the 12bits so each channel is 16bits. Then, I output my data as a Avalon-ST with 16bits per symbol and 8 symbols per beat. I made a signal called valid and just made it 1 all the time. Not sure if this is ok or not, and I made a ready, which is just an input that does nothing. Again, I am not sure this is correct, what should I do. So, now the SGDMA is expecting my symbols to be 8 bits....whats up with that? Also, I need to change my symbols into packets? Why? I don't know. Any help on this whole setup would be greatly appreciated.