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Altera_Forum's avatar
Altera_Forum
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16 years ago

lpm_fifo instatiation: Logic Elements not consumed

Hello,

I am using the Megawizard module lpm_fifo in my design which gave me strange problem.

I have a lpm_fifo in my design whose output (8 bits) q_o[7..0] is routed to another module.

fifo0.bmp is the lpm_fifo module I used in my design. It is a 64 word x 8 bit Fifo which should atleast consume 64x8 = 512 Logic Elements(LE). But, strangely it is just consuming 17 LE for the whole lpm_fifo.

I started debugging it by removing all the signal connections and connecting input-output pins to it in which case lpm_fifo is cosuming >512 LE. Finally I could trace it down to the pin q_o[7..0] which is causing the problem. If I connect a output pin to it, my design takes >512 LE. In first case it is not consuming the required number of LE.

any help is appreciated

:confused:

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    With most FPGA families, the FIFO should be expected to use internal RAM rather than LEs, unless you explicitely select a logiccell implementation.

    However, when not output signals depend on the FIFO module, respectively it has no effective input or clock, it will be always removed by the fitter.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    With most FPGA families, the FIFO should be expected to use internal RAM rather than LEs, unless you explicitely select a logiccell implementation.

    However, when not output signals depend on the FIFO module, respectively it has no effective input or clock, it will be always removed by the fitter.

    All the fifo pins are connected with other modules. Please refer to fifo0.bmp and fifo1.bmp
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    These schematics don't clarify anything. They show only signal names, no input or output pins.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Sorry for not providing with enough information.

    referring to top_usb_sd.jpg attached with this post,

    right bottom corner is my lpm_fifo

    right top corner is USB_interface

    above lpm_fifo is sdio_capture module

    output from sdio_capture is data input to lpm_fifo

    output from lpm_fifo is data input to usb_interface
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    To dropdown the problem to the minimum level,

    A quartus II project with a lpm_fifo (64 bytes) instatiated in top level .bdf with fifo output (q[7..0]) connected to a output pin is consuming 647 LE which is acceptable as it needs 512 LEto store 64 bytes (64 * 8).

    Whereas, fifo output (q[7..0]) left with no connection or just connected with a bus is consuming only 20 LE

    anybody had this problem before???

    i have attached the complete project if anybody wants to give a try. by the way, i am working on quartus ii 8.1 build 163 web edition. device selected is maxii 1270 series cpld.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Unfortunately, the example doesn't clarify, how the FIFO is connected in the design. Of course it is implemented, when connected directly to pins.

    --- Quote Start ---

    Whereas, fifo output (q[7..0]) left with no connection or just connected with a bus is consuming only 20 LE

    --- Quote End ---

    That's what I already said before

    --- Quote Start ---

    However, when not output signals depend on the FIFO module, respectively it has no effective input or clock, it will be always removed by the fitter.

    --- Quote End ---

    It's obvious, that the FIFO will be removed during synthesis, if the FIFO output is left with no connection. The more interesting question is, what means connected with a bus? If the FIFO output is influencing output signals indirectly through the bus, the FIFO is synthesized. Regarding your original question, if you expect, that the FIFO would used in the design, but the fitter removes it, you have proved, that the FIFO output is actually not used in your design, most likely due to a coding error.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    thanks for making it clear about Fifo synthesis and fitter replacements.

    --- Quote Start ---

    what means connected with a bus? If the FIFO output is influencing output signals indirectly through the bus, the FIFO is synthesized.

    --- Quote End ---

    I will drag a bus line from q[7..0] and name it FifoDout[7..0] and connect it it input of another module. Logically, fitter should be able to produce LEs for this connection. Unfortunately not. Which is my problem that needs to be resolved
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    To see the FIFO LE actually implemented, the "other module" which it's connected to, must influence any output pins. There are other means to keep LEs in special cases. By default, Quartus assumes, that you are targetting to a real design, where you won't keep any "dead" LEs.