Forum Discussion
Altera_Forum
Honored Contributor
16 years agoWith most FPGA families, the FIFO should be expected to use internal RAM rather than LEs, unless you explicitely select a logiccell implementation.
However, when not output signals depend on the FIFO module, respectively it has no effective input or clock, it will be always removed by the fitter. All the fifo pins are connected with other modules. Please refer to fifo0.bmp and fifo1.bmp