Low Pass Frequency Filter in Verilog

You could use signaltap to check what your system is doing.

While I'm not a Verilog specialist, I see that you use one bit of your 'in' vector as a clock, and this isn't a good idea. You could have metastability issues between your two always blocks, and your second block is sensitive to glitches. Your design would be a lot safer if you could include both parts inside the always @(posedge clk) block, and for example detect a falling edge on in[11] by comparing the signal to it's previous value.

Here is my new code:

module filter(in,out,clk);

input signed [11:0] in;

output signed [13:0] out;

input clk;

wire [13:0]out;

reg [17:0]counter;

reg q;

reg [11:0]t;

assign out=(~in & t) <<< 2;

always @(posedge clk) begin

if(counter[17]==0) counter=counter+1;

if((q==0) & (in[11]==1)) begin q=in[11];

t={counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17]};

counter=18'b000000000000000000;

end

if((q==1) & (in[11]==0)) q=in[11];

end

endmodule

The output is still 0.... what do I do wrong?

The new code is working great for lower bites...(if you set the controlling bite of the counter 12 for example) but it seems not to work that great for 15,16,17... the output is just 0. Can someone explain why??? Moreover the output is still zero for frequencies as 1khz even if the counter is set on the 12th bite, but it works perfectly in the range higher than that.

Thanks

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Here is my new code:

module filter(in,out,clk);

input signed [11:0] in;

output signed [13:0] out;

input clk;

wire [13:0]out;

reg [17:0]counter;

reg q;

reg [11:0]t;

assign out=(~in & t) <<< 2;

always @(posedge clk) begin

if(counter[17]==0) counter=counter+1;

if((q==0) & (in[11]==1)) begin q=in[11];

t={counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17]};

counter=18'b000000000000000000;

end

if((q==1) & (in[11]==0)) q=in[11];

end

endmodule

The output is still 0.... what do I do wrong?

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in my opinion you should assign the counter to : counter <= counter + 1 , the register counter is a D ff and it is under , in this case you are specified the edge-sensitive behavior of the circuit (posedge clk) so you have to put the none-Blocking (<= )assignments for your registers .

It is supposed to do the following:

If the frequency of the input is lower or equal than the threshold frequency the output will look exactly as the input,

else the output will be 0.

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It is supposed to do the following:

If the frequency of the input is lower or equal than the threshold frequency the output will look exactly as the input,

else the output will be 0.

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and what is the nature of your input(sine waves or any signal). Your filter sounds ideal pass/not pass but yo haven't explained your algorithm.

How you going to detect frequency of input?

Yeah... I think you are right, and I should explain a little bit more about the idea of the code.

The input is a sine wave. The design will be implemented on a Altera Cyclone FPGA, installed on a USRP. The input clock has a frequency of 64Mhz. The input signal is compared to a counter(whose frequency I can change... knowing the frequency of the clock). At every time that input goes from positive value to negative(we use the 2's complement properties here... and exactly the fact that if the signal is negative the first bit is 1 and if positive the first bit is 0) the control wave is restored to 0 and the comparison between the input signal and the control one is done one more time.

Hope this helps,

Sorry for not doing it from the start.

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Yeah... I think you are right, and I should explain a little bit more about the idea of the code.

The input is a sine wave. The design will be implemented on a Altera Cyclone FPGA, installed on a USRP. The input clock has a frequency of 64Mhz. The input signal is compared to a counter(whose frequency I can change... knowing the frequency of the clock). At every time that input goes from positive value to negative(we use the 2's complement properties here... and exactly the fact that if the signal is negative the first bit is 1 and if positive the first bit is 0) the control wave is restored to 0 and the comparison between the input signal and the control one is done one more time.

Hope this helps,

Sorry for not doing it from the start.

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OK, so your sine input is running at system clock of 64MHz and for sine threshold of 500Hz you need to count up to 64000 (on 64MHz clock) for half cycle to see if sign bit changes(zero crossing) then pass it if so or more than 64000 clocks else mute it. Naturally you need to count 1/2 cycle and decide and may be you don't need to store that first half i.e. is it one check only to decide or you keep tracking your input in which case you need to store each half before deciding.

My simplest algorithm would be: run counter 0 ~ 64000-1, checking sign bit regularly. if sign bit didn't change right to end pass input else mute.

Thus you need first to determine the algorithm before writing code. We are also ignoring phase of sine input.

Thanks kaz... though, can you please explain what is the disadvantage of checking the whole period of the input instead of checking only one half?

Thanks