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Altera_Forum
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13 years ago

Low Pass Frequency Filter in Verilog

Hello, I am trying to implement a low pass frequency filter in Verilog. I know that the input is a sine wave that oscilates around 0. The threshold is 500hz. Here is my code: module filter(clk,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The new code is working great for lower bites...(if you set the controlling bite of the counter 12 for example) but it seems not to work that great for 15,16,17... the output is just 0. Can someone explain why??? Moreover the output is still zero for frequencies as 1khz even if the counter is set on the 12th bite, but it works perfectly in the range higher than that.

Thanks