--- Quote Start ---
Here is my new code:
module filter(in,out,clk);
input signed [11:0] in;
output signed [13:0] out;
input clk;
wire [13:0]out;
reg [17:0]counter;
reg q;
reg [11:0]t;
assign out=(~in & t) <<< 2;
always @(posedge clk) begin
if(counter[17]==0) counter=counter+1;
if((q==0) & (in[11]==1)) begin q=in[11];
t={counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17]};
counter=18'b000000000000000000;
end
if((q==1) & (in[11]==0)) q=in[11];
end
endmodule
The output is still 0.... what do I do wrong?
--- Quote End ---
in my opinion you should assign the counter to : counter <= counter + 1 , the register counter is a D ff and it is under , in this case you are specified the edge-sensitive behavior of the circuit (posedge clk) so you have to put the none-Blocking (<= )assignments for your registers .
Honored Contributor
