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Altera_Forum's avatar
Altera_Forum
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11 years ago

Latch Inferred Help

Hi everyone.

I have a code in Verilog, wich must be combinational, but I can't figure out how to make it without creating a latch.

The logic is correct, and simulates fine, but I'd like to remove the latch. 

module locker
(
 input       wire   INPUT,
 output reg                lock    
 );
 localparam high_low_threshold = 16'b00000001_10011001; 
 localparam low_high_threshold = 16'b00000100_00000000;
 
always @ ( * )
begin
        lock = 1'b0;
    if (INPUT >= low_high_threshold)
        lock = 1'b1;
    else if (INPUT < high_low_threshold)
        lock = 1'b0;
        
end
endmodule

Thank You!!

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    i'm not really sure in verilog, but the first 

    lock = 1'b0

    seems wrong to me.

    if you walk through the code, you assign the output lock twice. So your logic don't exactly know what to do.

    I think you have to move this into the "else" path of the second if. By this way this default-assignment will only be done, if the other two if-cases don't occure.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    try using non-blocking assignments with <= assignment, rather than blocking.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The shown code doesn't generate a latch, neither with blocking nor nonblocking assignments.

    --- Quote Start ---

    seems wrong to me.

    --- Quote End ---

    The default assignment lock = 1'b0 is required to avoid a latch.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I'm more into VHDL. If you assign two different values in one walk through there, you will surely get unexpected behaviour.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The code shows the variable will take one value - 1 or 0. The top value is the default value if the other two situations do not occur.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    I'm more into VHDL. If you assign two different values in one walk through there, you will surely get unexpected behaviour.

    --- Quote End ---

    No unexpected behaviour, neither in Verilog nor VHDL.

    Multiple assignments in sequential code (Verilog always block or VHDL process) are pretty legal. In case of VHDL signals and non-blocking Verilog assigments, only the last assignment will take effect. In case of VHDL variables or Verilog blocking assignments, previous assignments matter, if they are read during the sequential code. In any case, the final assignment will be kept until next schedule of the sequential code.

    Multiple assignments in concurrent code, including assignments to the same variable/signal in different sequential blocks cause a "multiple driver" error in hardware synthesis.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    @rafael_kl

    Why do you think the latch is created in the first place.