Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Latch Inferred Help

Hi everyone. I have a code in Verilog, wich must be combinational, but I can't figure out how to make it without creating a latch. The logic is correct, and simulates fine, but I'd like to re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

i'm not really sure in verilog, but the first 

lock = 1'b0

seems wrong to me.

if you walk through the code, you assign the output lock twice. So your logic don't exactly know what to do.

I think you have to move this into the "else" path of the second if. By this way this default-assignment will only be done, if the other two if-cases don't occure.