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Altera_Forum
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11 years ago

Latch Inferred Help

Hi everyone. I have a code in Verilog, wich must be combinational, but I can't figure out how to make it without creating a latch. The logic is correct, and simulates fine, but I'd like to re...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The shown code doesn't generate a latch, neither with blocking nor nonblocking assignments.

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seems wrong to me.

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The default assignment lock = 1'b0 is required to avoid a latch.