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I'm more into VHDL. If you assign two different values in one walk through there, you will surely get unexpected behaviour.
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No unexpected behaviour, neither in Verilog nor VHDL.
Multiple assignments in sequential code (Verilog always block or VHDL process) are pretty legal. In case of VHDL signals and non-blocking Verilog assigments, only the last assignment will take effect. In case of VHDL variables or Verilog blocking assignments, previous assignments matter, if they are read during the sequential code. In any case, the final assignment will be kept until next schedule of the sequential code.
Multiple assignments in concurrent code, including assignments to the same variable/signal in different sequential blocks cause a "multiple driver" error in hardware synthesis.
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