Keypad Scanner help!

Hi, welcome to the dark side of VHDL if you are a software programmer !!! ;-)

PROCESS (clock_50)
BEGIN
IF rising_edge(clock_50) THEN -- clock signal
     IF pulse_10us = '1' then -- enable signal
          -- your sequential synchronous statements here
     END IF;
END IF;
-- absolutely nothing here
END PROCESS;

CASE Keypad_write IS
    WHEN "0111" => 
        If (Keypad_read = "0111" ) THEN
            LED<= "00000001";
        ELSIf (Keypad_read = "1011") THEN
            LED<= "00000100";
        ELSIf (Keypad_read = "1101") THEN
            LED<= "00000111";
        END IF;
    WHEN .... => ....
    WHEN OTHERS => ....
END CASE;

Thanks alot for the great reply. I understand that VHDL is for describing hardware. My problem is that I have been writing so much software and now when I go to write VHDL , I am in the same mind frame ))

So here is my second attempt. It works better, but the correct values are displayed on the LEDs only when I keep the key pressed down. When I release, the value displayed is the one on the third column again on the same row. Does anyone know where I am still going wrong? Also, are there too many processes here? Could I have designed this a better way? Thanks very much for any help as I am just in the learning phase still with VHDL.

ARCHITECTURE behaviour of KeypadScanner IS
SIGNAL pulse_10us : STD_LOGIC;
SIGNAL count : INTEGER := 0;
SIGNAL Key_write : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0111";
BEGIN
Keypad_write<= Key_write;
----------------------------
PROCESS (clock_50)
BEGIN
If (clock_50'EVENT AND clock_50 = '1' ) THEN
	count<= count + 1;
	If (count = 500) THEN
		count<= 0;
	END IF;
END IF;
END PROCESS;
--------------------------------
PROCESS (clock_50)
BEGIN
If (clock_50'EVENT AND clock_50 = '1' ) THEN
	IF (count = 0) THEN
		pulse_10us<= '1';
	ELSIF (count = 1) THEN
		pulse_10us<= '0';
	END IF;
END IF;
	
END PROCESS;
-------------------------------------
PROCESS (clock_50)
BEGIN
If (clock_50'EVENT AND clock_50 = '1' ) THEN -- clock signal
     IF pulse_10us = '1' THEN -- enable signal
			If (Key_write = "0111") THEN
				Key_write<= "1011";
			ELSIF (Key_write = "1011") THEN
				Key_write<= "1101";
			ELSIF (Key_write = "1101") THEN
				Key_write<= "0111";
			END IF;
     END IF;
END IF;
END PROCESS;
--------------------------------------------
PROCESS (clock_50)
BEGIN
If (clock_50'EVENT AND clock_50 = '1' ) THEN -- clock signal
     IF pulse_10us = '1' THEN -- enable signal
			CASE Key_write IS
			 WHEN "0111" => 
				  If (Keypad_read = "0111" ) THEN
						LED<= "00000001";
				  ELSIf (Keypad_read = "1011") THEN
						LED<= "00000100";
				  ELSIf (Keypad_read = "1101") THEN
						LED<= "00000111";
				  END IF;
			 WHEN "1011" => 
				  If (Keypad_read = "0111" ) THEN
						LED<= "00000010";
				  ELSIf (Keypad_read = "1011") THEN
						LED<= "00000101";
				  ELSIf (Keypad_read = "1101") THEN
						LED<= "00001000";
				  END IF;
			WHEN "1101" => 
				  If (Keypad_read = "0111" ) THEN
						LED<= "00000011";
				  ELSIf (Keypad_read = "1011") THEN
						LED<= "00000110";
				  ELSIf (Keypad_read = "1101") THEN
						LED<= "00001001";
				  END IF;
        WHEN OTHERS => 
					LED<= "11111111";
		END CASE;
    END IF;
END IF;
END PROCESS;
------------------------------------------
END behaviour;

powerful you have become !

PROCESS (clock_50)
BEGIN
If (clock_50'EVENT AND clock_50 = '1' ) THEN
	-- it is a count down here
        -- produce pulse when reach 0
	If (count = 0) THEN -- little better to compare to 0
               count<= 500;
                pulse_10us <= '1';
        ELSE
                count <= count -1;
                 pulse_10us <= '0'
	END IF;
END IF;
END PROCESS;

I still don't understand why this is wrong. Initially, at the beginning of the Architecture , I initialise Keypad_write with "0111", so on the first clock cycle, the read process should read Keypad_write as "0111" and perform the correct action.? Then the next clock cycle after that, the write process would have previously changed Keypad_write to "1011" and so the read process will then process it. Could you please show me what I am doing wrong and how to resolve this? It's driving me mad. Help much appreciated. Thanks alot

YES YES YES ! with your previous code, you are right.

...
SIGNAL sig : std_ulogic_vector(3 downto 0) := "0000";
PROCESS (clk)
BEGIN
If rising_edge(clk) THEN
    sig <= "1010"; -- sig will be affected at the end on the process, so here at the first clk edge, 
    -- sig still equals to "0000" for this time !
    IF sig = "1010" then
        -- instructions here 
        -- that are NOT executed because sig = "0000"
        -- will be executed at the next clk edge
    ELSE
        -- instructions that will be executed the first time
    END IF;
END IF;
END PROCESS;

@Tricky : It is not important because it keeps the signals BUT can produce unwanted behaviour.

process(clk)
begin
  if rising_edge(clk) then
    if cnta = 10 then
      cntb <= cntb + 1;
    else
      cntb <= cntb;   --there is no point in this code. It makes NO difference to the behaviour.
    end if;
  end if;
end process;

I still can't see where I am going wrong.