Hi, welcome to the dark side of VHDL if you are a software programmer !!! ;-)
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VHDL is NOT a programming language. It describes hardware.
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1) Do you want you
code to be synthesized (and to be put on FPGA) ?
If so,
forget the clauses "after", they are simply ignored.
That why only the 3rd part of your code is "active", the others are simply optimized away, because Keypad_write will always be "1101" (You could find that in Quartus warning messages)
2) Make a
really synchronous process, in fact a D Flip Flop with Enable like that :
PROCESS (clock_50)
BEGIN
IF rising_edge(clock_50) THEN -- clock signal
IF pulse_10us = '1' then -- enable signal
-- your sequential synchronous statements here
END IF;
END IF;
-- absolutely nothing here
END PROCESS;
3) You need a signal that supplies 1 pulse whose width = clock_50 period, whose period is 10 us.
You can obtain that with a synchronous counter (quite easy to design, good exercise).
4) You need a one-hot counter ("0001" then "0010" then "0100" then "1000") simply by rotate one hot bit each 10us (= the above Enable signal).
that you simply invert for "keyboard_write"
5) IMPORTANT
You don't cover all possible cases !!
6) Don't use multiple IF statements in a process, because the signals are affected by the last statement
In your case, you should use
CASE Keypad_write IS
WHEN "0111" =>
If (Keypad_read = "0111" ) THEN
LED<= "00000001";
ELSIf (Keypad_read = "1011") THEN
LED<= "00000100";
ELSIf (Keypad_read = "1101") THEN
LED<= "00000111";
END IF;
WHEN .... => ....
WHEN OTHERS => ....
END CASE;
Be strongly aware that there is a latence of 10us on Keyboard_write, so you need to insert one 10us Enable D Flip Flop on Keyboard_read