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Altera_Forum's avatar
Altera_Forum
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12 years ago

Keypad Scanner help!

Hi, I am new to VHDL. I am having issues implementing a 3 x 3 keypad scanner. The similar technique I have used in C code but it doesn't seem to work with VHDL. I scan each column by putting a log...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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@Tricky : It is not important because it keeps the signals BUT can produce unwanted behaviour.

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Assinging a signal in ALL cases in a clocked process can also produce unwanted behaviour, or just extra unwanted code.

I want to increment a counter only when another counter = 10 


process(clk)
begin
  if rising_edge(clk) then
    if cnta = 10 then
      cntb <= cntb + 1;
    else
      cntb <= cntb;   --there is no point in this code. It makes NO difference to the behaviour.
    end if;
  end if;
end process;