Is there any limitation of the sample clock of SignaltapII

Question

I remember that this clock can't be higher than 175Mhz, am i right? But, I used much higher than 175MHz clock as the sample clock of SiganltapII in many cases.

However, i met a problem when i used 200Mhz clock as signaltapII's sample clock. It seems that this clock is too higher to be used as signaltapII's sample clock, for i change it to 100Mhz would be ok.

The object device is ArriaGX. But i can use 200Mhz clock as signaltapII sample clock in CycloneII device on my another board. Why?

altera_forum · Answer

SignalTap II sampling mechanism and clock frequency is bound to correct synchronous timing as other design entities. If you are sampling signals in clock domains with known timing relation to the sampling clock, timing analysis will tell you about correct timing. But it can't for unrelated clock domains. Signals sampled from an unrelated clock domain are not becessarily consistent.

altera_forum · Answer

TimeQuest will analyze your design with SignalTap, so if it fails timing, you will know about it.  (If you sample logic from another clock domain, and have cut timing between that domain and the one SignalTap is using, then it naturally won't be analyzed).  It should be able to run 200Mhz without much difficulty.  It's little more than shift-registers sampling data and sending it into memory.  The logic levels are low, but the placement can be difficult.

altera_forum · Answer

Thanks you both reply!

Firstly, the project is almost same on my both board(CII&ArriaGX); Secondly, it can run when i change the ArriaGX's sample clock to 300Mhz. It's strange. The sample clock is the same output of PLL, I just change the PLL's setting to change the frequency from 200 to 300Mhz.

altera_forum · Answer

Sounds like you'll need to run SignalTap to debug the existing SignalTap.   (Sorry, I couldn't resist...)

altera_forum · Answer

I attached 2 jpg file.

The first is my PLL, c3 output is as my signaltap's sample clock. c0 and c1 are 100Mhz output. c2 is 40Mhz, c4 is 10Mhz.

I add c0,c2 and c4 into signaltap, when setting c3 to 200Mhz, the signaltap didn't work as attached file shows. But when setting c3 to 300Mhz, the signaltap run well.

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Is there any limitation of the sample clock of SignaltapII

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