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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is there any limitation of the sample clock of SignaltapII

I remember that this clock can't be higher than 175Mhz, am i right? But, I used much higher than 175MHz clock as the sample clock of SiganltapII in many cases. However, i met a problem when i u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks you both reply!

Firstly, the project is almost same on my both board(CII&ArriaGX); Secondly, it can run when i change the ArriaGX's sample clock to 300Mhz. It's strange. The sample clock is the same output of PLL, I just change the PLL's setting to change the frequency from 200 to 300Mhz.