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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is that possible to pause a system?

In a design, I try to use a FIFO to build a handshake interface between two clock domains to transfer data. However, read rate can not grantee that its rate is higher than write. Therefore, in some cases the full signal will be enabled, and the system should be paused until the full signal in FIFO be disabled. In this system, the data will be processed (do arithmetic calculation ) in pipeline and there are PLLs in design, is that possible to pause the system when the full signal of FIFO is enabled? I don't know whether pausing the toggle of clock will work or not.

Thanks very much.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    if you 'pause' the clock, it means that you are going to implement a gated clock which is highly not recommended by most of the digital system design. add a "clock enable" signal in your design to determine when your design should run and when it should pause.

    adding on, you might want to consider using "almost full" or "almost empty" port to control your design if you experience some data loss.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    if you 'pause' the clock, it means that you are going to implement a gated clock which is highly not recommended by most of the digital system design. add a "clock enable" signal in your design to determine when your design should run and when it should pause.

    adding on, you might want to consider using "almost full" or "almost empty" port to control your design if you experience some data loss.

    --- Quote End ---

    Yes，I think using a "almost full" is necessary since "enable" in module usually does not pause the system soon, it has delay. And I need make all the modules in my design has enable, including my customized design module.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If your read rate is lower than your write rate, then there is something fundamentally wrong with your design. Using the almost full will only help if you can actually halt the data flow, otherwise data will be lost. You can use the almost full as part of the clock enable for the upstream devices.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    If your read rate is lower than your write rate, then there is something fundamentally wrong with your design. Using the almost full will only help if you can actually halt the data flow, otherwise data will be lost. You can use the almost full as part of the clock enable for the upstream devices.

    --- Quote End ---

    Yes, you are right. For a stable system, read rate should grantee higher than write. Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Yes, you are right. For a stable system, read rate should grantee higher than write. Thanks

    --- Quote End ---

    No that is not right. What goes in must come out i.e. rate_in = rate_out. But rate is time dependent. It is common practice to process bursty data flow using fifo to give elasticity(buffering like water tank) but the rate of fifo_in should tend to be same as data_out over longer segment of time. In these cases it is better to set fifo operating point at some optimum point e.g. half full so that if you run out of input the fifo will supply and if there is a burst of data then fifo has space for it. You will also need an alarm flag just in case.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    No that is not right. What goes in must come out i.e. rate_in = rate_out. But rate is time dependent. It is common practice to process bursty data flow using fifo to give elasticity(buffering like water tank) but the rate of fifo_in should tend to be same as data_out over longer segment of time. In these cases it is better to set fifo operating point at some optimum point e.g. half full so that if you run out of input the fifo will supply and if there is a burst of data then fifo has space for it. You will also need an alarm flag just in case.

    --- Quote End ---

    Thanks very much, kaz. What is 'alarm flag' used for? To warn the fifo is full?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The alarm flag is to be set if fifo gets empty or full. During system development you will then need to readjust the operating point or fifo size until the alarm disappears but keep it in the delivered design so that your manager wouldn't sack you in case the design fails in field.

    The processing behind fifo will continue nonstop and there is no need to pause the flow.

    If your flow is packet based then you need to be careful not to break packet boundary in the fifo. Some system allow inserting null data in case it is needed when flow is too slow.