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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is that possible to pause a system?

In a design, I try to use a FIFO to build a handshake interface between two clock domains to transfer data. However, read rate can not grantee that its rate is higher than write. Therefore, in some c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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If your read rate is lower than your write rate, then there is something fundamentally wrong with your design. Using the almost full will only help if you can actually halt the data flow, otherwise data will be lost. You can use the almost full as part of the clock enable for the upstream devices.

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Yes, you are right. For a stable system, read rate should grantee higher than write. Thanks