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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is that possible to pause a system?

In a design, I try to use a FIFO to build a handshake interface between two clock domains to transfer data. However, read rate can not grantee that its rate is higher than write. Therefore, in some c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

if you 'pause' the clock, it means that you are going to implement a gated clock which is highly not recommended by most of the digital system design. add a "clock enable" signal in your design to determine when your design should run and when it should pause.

adding on, you might want to consider using "almost full" or "almost empty" port to control your design if you experience some data loss.