Altera_Forum
Honored Contributor
Honored ContributorIP Regeneration Policy - Quartus Prime Lite 15.1
What has happened to IP regeneration policy? In the past, I could compile my QSYS or SOPC Builder system, and then compile my FPGA. And the FPGA build would use the result of the last Qsys/SOPC Builder build. These days, with Quartus Prime, there is an "IP regeneration policy" which has two options - "Always regenerate synthesis files for IP cores" and "Never regenerate synthesis files for IP cores". Unfortunately the latter is greyed out, and the former is the only thing you can select. Changing the setting in the QSF file doesn't help either - it ignores it!
My issue is that I have a DDR3 hard memory interface in my Cyclone V design, built with Qsys. It takes over 10 minutes to generate the Qsys model for synthesis. So when I hit Generate HDL in Qsys I wait 10 minutes and it's done. And then I hit compile in Quartus and it does it all again. Even if I don't touch the Qsys file, it ALWAYS spends over 10 minutes rebuilding the Qsys system. And, to make matters even worse, if I compile a new file into my project, and have a syntax error in my file, Analyse Current File doesn't spot it, so I hit "Start Compilation" and it spends 12 mintues rebuilding the Qsys system and THEN checks the new file and says - "Ooops, you messed up there and I can't get any further". This is a HUGE waste of time. Can the tool be changed to stop regeneration of IP UNLESS the files have changed? Please?
