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Altera_Forum
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10 years ago

IP Regeneration Policy - Quartus Prime Lite 15.1

What has happened to IP regeneration policy? In the past, I could compile my QSYS or SOPC Builder system, and then compile my FPGA. And the FPGA build would use the result of the last Qsys/SOPC Bui...
Altera_Forum's avatar
Altera_Forum
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10 years ago

I'm using a PC with i7+32GB DDR4 RAM+SSD and Qsys is still a slow beast. But then the Qsys project I'm working on has 50 subsystems and 131 custom IP cores, so fairly large! It takes about 15 minutes to generate the HDL from Qsys - takes 5 minutes and uses ~2GB of RAM just to open it!

As the versions go on Qsys seems to get slower and more bloated so I doubt updating the PC will help much if you already have 8GB of RAM. Compile times with the larger FPGAs may be reduced (for the Stratix V's they recommend 16GB of RAM for compiling).