Occasional ContributorI/O Register Packing
Hello,
I wanted to get a conceptual understanding of how I/O Register Packing works. I was reading the Intel® Quartus® Prime Standard Edition User Guide: Design Compilation version 2018.09.24 and section 1.10.13 talks about I/O Register Packing when it comes to cross-partition register packing of I/O registers.
I have found the definition for register packing. I understand I/O Register Packing to work by taking the register that is connected to an input or output of a pin of the device and moving it to be contained in the I/O Cell (I/O Element) near the periphery of the device instead of a Logic Element (LE).
Is that a correct assessment?
When it comes to cross-partition register packing, does that mean that Quartus will break the partition boundaries to attempt to do what I described above?
Thank you ahead of time for any clarification!
THZ
Your assessment is correct.
When you are talking about "cross-partition register packing", I assume you are talking about design partitioning. This part of the user guide explains it: https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/i-o-register-packing.html
