I/O pins located in a block

Hello,

I have a very simple problem :

I would like to map some of the I/O pins of the FPGA, which are connected to a wide external bus (hsma_d[75..0]) on a commercial board, to an internal bus (AD_A[13..0], AD_B[13..0], ...)

thus, for an example, I connected just by mapping inside a .brd file, the data coming from the ADC bus on the HSMA connector to the DAC bus on the same HSMA connector (but other pins obviously). the project compilation is fine and I am able with a signal generator and a scope, to compare the signal sent to the ADC with the one obtained from the DAC.

thus the principle is OK.

then, I would like to hide this I/O pins mapping inside blocks to avoid to show all these pins at the top level, which is not a very interesting information.

then I create a block in which I make exactly the same mapping and I connect this block at the top level.

the advantage is, from the top level, one sees only boxes (ADC, DAC, ...) with a "clean" bus (only one wire) and not plenty of pins.

BUT in this case, Quartus is not able to properly connect the I/O pins declared inside the blocks despite the fact that the assignment editor seems happy (all status are OK).

then my questions are :

is it possible in Quartus to declare I/O pins of the FPGA directly inside blocks ?

and if yes, how to do that properly ?

thank you for your help

best regards

ronic