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Altera_Forum
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11 years ago

I/O pins located in a block

Hello, I have a very simple problem : I would like to map some of the I/O pins of the FPGA, which are connected to a wide external bus (hsma_d[75..0]) on a commercial board, to an internal b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Well there is at least one reason I can think of why it is not implemented. How does the compiler know that your clock or reset port in a component shouldn't be mapped to a pin? Changing those names is not always an option as you frequently use off-the-shelf code.