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TKlei11's avatar
TKlei11
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2 years ago

Intel LVDS Serdes Receiver removed input pins after compilation

Hi,

I'm trying to read out data from an 12 bit LVDS ADC using the Intel LVDS SERDES IP.

The IP is configured as a 9 channel RX DPA-FIFO with an Serdes Factor of 6. I'm using bit slip for alignment.

I can't get it working due to optimizations in Quartus during compilaton. A lot of the registers are reduced due to "stuck datain" and so after A & S these messages appeare:

Warning (21074): Design contains 9 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "adc_fclk_0_i"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[0]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[3]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[5]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[2]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[7]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[1]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[4]"
Warning (15610): No output dependent on input pin "adc_rxin_0_i[6]"

The input pins of the board are connected to the lvds serdes rx_in pins. The external clock from the ADC is connected to the inclock of the IP.

The IP is instantiated in a wrapper component (ip/adc_out), which controls the bit slip and creates 12 bit signals after receiving two 6 bit signals form the IP.

Im working on this problem for a few days now and can't find a solution. I've attached the project (Quartus Prime Standard 21.1) . Do you have any clue what causes this optimization?

Thanks & Best,

Thomas

Compilation
Hdl

2 Replies

  • TKlei11's avatar
    TKlei11
    Icon for New Contributor rankNew Contributor
    2 years ago

    Additional note: After disabling bit slip in the SERDES IP it seems to work. However I need the alignment.

    I'm using the following state machine for handling the bit slip:

    proc_bitslip: process(rx_coreclock, rst_i)
    begin
    if rst_i = '1' then
    bitslip_ctrl <= (others => '0');
    bitslip_rst <= (others => '1');
    bsctrl_state <= idle;
    frame_locked <= '0';
    elsif rising_edge(rx_coreclock) then
    bitslip_ctrl <= (others => '0');
    bitslip_rst <= (others => '0');
    case bsctrl_state is
    when idle =>
    if rx_out(53 downto 48) /= "111111" or rx_out(53 downto 48) /= "000000" then -- sync pattern
    bitslip_ctrl <= (others => '1'); --pulse bit slip ctrl
    bsctrl_state <= wait0;
    frame_locked <= '0';
    else
    frame_locked <= '1';
    end if;
    when wait0 =>
    bsctrl_state <= wait1;
    when wait1 =>
    bsctrl_state <= wait2;
    when wait2 =>
    bsctrl_state <= wait3;
    when wait3 =>
    bsctrl_state <= idle;
    when others =>
    bsctrl_state <= idle;
    end case;
    end if;
    end process;