Additional note: After disabling bit slip in the SERDES IP it seems to work. However I need the alignment.
I'm using the following state machine for handling the bit slip:
proc_bitslip: process(rx_coreclock, rst_i)
begin
if rst_i = '1' then
bitslip_ctrl <= (others => '0');
bitslip_rst <= (others => '1');
bsctrl_state <= idle;
frame_locked <= '0';
elsif rising_edge(rx_coreclock) then
bitslip_ctrl <= (others => '0');
bitslip_rst <= (others => '0');
case bsctrl_state is
when idle =>
if rx_out(53 downto 48) /= "111111" or rx_out(53 downto 48) /= "000000" then -- sync pattern
bitslip_ctrl <= (others => '1'); --pulse bit slip ctrl
bsctrl_state <= wait0;
frame_locked <= '0';
else
frame_locked <= '1';
end if;
when wait0 =>
bsctrl_state <= wait1;
when wait1 =>
bsctrl_state <= wait2;
when wait2 =>
bsctrl_state <= wait3;
when wait3 =>
bsctrl_state <= idle;
when others =>
bsctrl_state <= idle;
end case;
end if;
end process;
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