Instantiation Components Compile error

Hi,

I'm new to Quartus 6.1 Web Edition software. I bought the CYCLONE FPGA Starter Board and tries to learn how to use Quartus 6.1 that came with the board.

The problem I'm having is with my functions, parts and component libraries. For example, when I try to compile the following VHDL code which is a FULL_ADDER, I keep getting the following error message :

vhdl error at full_adder.vhd(18): object "xor_3" is used but not declared

Before compiling the code, I've included the necessary libraries during the project creation. Despite everything I've tried, I'm still getting the same error message. It does not matter whether I include or not the use clauses for the libraries needed in my root page, I get the same error message. It just does not see my instantiated components.

I've to stress that the same code compiles and runs on ORCAD FPGA Simulation, but not on QUARTUS. Why is it so difficult to get things run normally with Quartus while they run smootly on all other simulators I've been working on so many years? - Strange...

I've followed all Quartus recommandations on the subject and I'm still anable to solve this issue.

Thanks to show me what to do in order to use my libraries with QUARTUS. Below is the program without the parts and components libraries needed.

library ieee;

use ieee.std_logic_1164.all;

-- I do not have to use the parts and components libraries below with ORCAD.

--library parts_lib;

--use parts_lib.all;

--library comp_pkg;

--use comp_pkg.all;

----------------------------------------------------------------------

entity full_adder is

port(

a, b, cin : in std_logic;

sum, co : out std_logic

);

end full_adder;

----------------------------------------------------------------------

architecture full_adder_arch of full_adder is

signal sig1, sig2, sig3 : std_logic;

begin

U1 : component xor_3 port map(

x1 => a, x2 => b, x3 => cin,

y => sum

);

U2 : component and_2 port map(

x1 => a, x2 => b,

y => sig1

);

U3 : component or_2 port map(

x1 => a, x2 => b,

y => sig2

);

U4 : component and_2 port map(

x1 => sig2, x2 => cin,

y => sig3

);

U5 : component or_2 port map(

x1 => sig1, x2 => sig3,

y => co

);

end full_adder_arch;