Forum Discussion
Altera_Forum
Honored Contributor
17 years agoYou must not necessarily use two process blocks, but it improves readability, I think.
As you previously mentioned, you can't have dual-edge sensitive registers. So you need separate registers for both edges and asynchronous logic to combine both register outputs. There are classical examples as factor 2.5 clock dividers. Some precaution is necessary to avoid glitches in this kind of design.