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Altera_Forum
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18 years ago

Instantiation Components Compile error

Hi, I'm new to Quartus 6.1 Web Edition software. I bought the CYCLONE FPGA Starter Board and tries to learn how to use Quartus 6.1 that came with the board. The problem I'm having is with ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The restriction basically isn't by Quartus but by the FPGA hardware. It's similar with any other vendors FPGA or ASIC. The only unrestricted usage of HDL is in simulation. Here you can define delays without needing a clock or design dual-edge sensitive registers.

To my opinion, it's important to understand how a HDL construct can be inferred in FPGA hardware, cause it helps you to avoid such constructs, that behave different in simulation and synthesis.