Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Instantiation Components Compile error

Hi, I'm new to Quartus 6.1 Web Edition software. I bought the CYCLONE FPGA Starter Board and tries to learn how to use Quartus 6.1 that came with the board. The problem I'm having is with ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Another way could be to use two separate process blocks as follows

------------------------------------------------

ARCHITECTURE arc OF test1 IS

begin

process (C)

begin

if (C'EVENT and C='1') then

if V='0' then

A <= '1';

else

A <= '0';

end if;

end if;

end process;

process (C)

begin

if (C'EVENT and C='0') then

end if;

end process;

end arc;

------------------------------------------------

Of course you will have to fill in the suitable sequential statements in the last if block.