Incremental Place and Route

Timing Constraints are considered the way to go, because a) they guide the fitter in it's choices and b) they give clear feedback on whether constraints were made or not. Just because some logic was placed close to some other logic, you still have no idea if it really met timing.

What skew can you handle? I haven't seen that posted, and it could make a huge difference. Also, what are the clock rates? If this is something where you can physically control with signals and probes, then it's probably slow enough that it doesn't matter. Since that uses the JTAG port, it clocks the data in serially and then does one clock to do a parallel transfer(I haven't looked at it, but assume this is the way it works), which is mighty slow. And you can constrain your clocks as so:

Look at the middle example of:

http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html

Just make it 3 clocks. Of course, if you're just switching between asynchronous clocks you will have clock glitches. That's one of the major reasons everyone is so against this. If you can, either disable all the logic while switching(perhaps have a clock enable).

Rysc:

Thanks, I’m reading this information.

bye

Ignacio

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Rysc:

Thanks, I’m reading this information.

bye

Ignacio

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Hi Ignacio,

maybe now I got what you are doing with the SP-Block. You have in your design some inputs dangling and you are stimulating these inputs with the SP-Block ??? What is the purpose of this input, when you have no input signal for them ?

But why do you have a skew problem with the clock ? You always use only one clock at time, so where is the problem. Of course have to constraint them like Rysc described in his post.

Hi Pletz

The purpose of the block SP is connect the design with a PC, because I have 10 binary inputs and I haven’t 10 switches on the board.

Yes, I only use one clock at time, but the output needs that the skew of this signal be almost 0.

Thanks Pletz

Ignacio

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Hi Pletz

The purpose of the block SP is connect the design with a PC, because I have 10 binary inputs and I haven’t 10 switches on the board.

Yes, I only use one clock at time, but the output needs that the skew of this signal be almost 0.

Thanks Pletz

Ignacio

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Hi Ignacio,

I don't know your design, but when I assume that your design uses one clock at time and is synchronous, you only could have a problem in your input ( setup times) or output ( clock to output) timing. Why do you need a skew of almost 0 ? Is it a requirement of the input or output timing ?

Kind regards

GPK

Hi Pletz,

The problem is in the output signal, because it use one of the clock at time, and this clock is select for the inputs. So in the output you can see the deferens between the clocks, hence if this deferens are different that I want, so is wrong.

I hope the explanation was clear.

Thanks Pletz

Ignacio.

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Hi Pletz,

The problem is in the output signal, because it use one of the clock at time, and this clock is select for the inputs. So in the output you can see the deferens between the clocks, hence if this deferens are different that I want, so is wrong.

I hope the explanation was clear.

Thanks Pletz

Ignacio.

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Hi Ignacio,

I don't get want mean. Is it possible to post a small drawing of your design to get an overview. Sorry that I'm not able to get it without it.

Kind regards

GPK

Hi Pletz I'm sorry. I was searching the authors of the paper that I used but they don’t answer my mails. My idea was give you this paper so you can understand the problem perfectly.

If they respond me I’ll tell you.

Merry Christmas and Happy New Year.

Thank you

Adios

Ignacio.

Hi everyone, I have an answer for the authors of the paper and you can see it in:

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4712525&arnumber=4663501&count=59&index=51

Thanks Sr Angel de Castro

Adios.

Ignacio.

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Hi everyone, I have an answer for the authors of the paper and you can see it in:

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4712525&arnumber=4663501&count=59&index=51

Thanks Sr Angel de Castro

Adios.

Ignacio.

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Hi Ignacio,

unfortunately I have no access to the document without buying it. What I could see in the summary was that they used a XILINX FPGA which includes a DLL. It looks tome that they used the DLL in there design.