Incremental Place and Route

Timing Constraints are considered the way to go, because a) they guide the fitter in it's choices and b) they give clear feedback on whether constraints were made or not. Just because some logic was placed close to some other logic, you still have no idea if it really met timing.

What skew can you handle? I haven't seen that posted, and it could make a huge difference. Also, what are the clock rates? If this is something where you can physically control with signals and probes, then it's probably slow enough that it doesn't matter. Since that uses the JTAG port, it clocks the data in serially and then does one clock to do a parallel transfer(I haven't looked at it, but assume this is the way it works), which is mighty slow. And you can constrain your clocks as so:

Look at the middle example of:

http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html

Just make it 3 clocks. Of course, if you're just switching between asynchronous clocks you will have clock glitches. That's one of the major reasons everyone is so against this. If you can, either disable all the logic while switching(perhaps have a clock enable).