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Altera_Forum's avatar
Altera_Forum
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13 years ago

incorrect variables synthesis or expected behavior for simple adder function

Sorry if this is redundant or stupid, I was not able to find similar question on the forum or even Google.

Actually, Google yielded some thread where the below code is quoted as a valid example of variables use for synthesis.

Given very simple VHDL code:

===========================================

library ieee;

use ieee.std_logic_1164.all;

entity toplevel is

port

(

a,b : in std_logic_vector(3 downto 0);

c,d : out std_logic_vector(3 downto 0)

);

end entity;

architecture rtl of toplevel is

function plus_s_s (a,b : std_logic_vector) return std_logic_vector is

variable s: std_logic_vector(a'range);

variable carry: std_logic;

begin

carry := '0';

for i in a'low to a'high loop

s(i) := (a(i) xor b(i)) xor carry;

carry := ((a(i) or b(i)) and carry ) or (a(i) and b(i));

end loop;

return s;

end;

begin

c <= plus_s_s(a,B"0001");

d <= plus_s_s(a,b);

end rtl;

===========================================

Results in proper "hand-made" adder for d output,

but for c output, instead of generating logic to increment a input, it generates c <= a

I'm attaching RTL view and this .vhdl

this happens on Quartus 12.1 build 177 for Linux, using Cyclone V device EP4CE115F29C7

Thank you for any help on insights.

V.L.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Actually, output c is (!a[3],a[2..0]) which is correct.

    A 'free' double-quoted string produces a std_logic_vector(0 to n), setting bit(3) to one

    The following code will translate correctly: 

    Constant ONE : std_logic_vector(3 downto 0) := b"0001" ;
c <= plus_s_s(a, ONE);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    This is what I got from the Windows version

    for this code: 

    library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
    port 
    (
        a,b  : in std_logic_vector(3 downto 0);
        c,d    : out std_logic_vector(3 downto 0)
    );
end entity;
architecture rtl of toplevel is
   function plus_s_s (a,b : std_logic_vector) return std_logic_vector is
        variable s: std_logic_vector(a'range);
        variable carry: std_logic;
    begin
        carry := '0';
        for i in a'low to a'high loop
            s(i) := (a(i) xor b(i)) xor carry;
            carry := ((a(i) or b(i)) and carry ) or (a(i) and b(i));
        end loop;
        
        return s;
    end;
    
Constant ONE : std_logic_vector(3 downto 0) := b"0001" ;
begin
    
    --c <= plus_s_s(a,B"0001");
    c <= plus_s_s(a,ONE);
    d <= plus_s_s(a,b);
    
end rtl;

    Perhaps you can post your source code?

    https://www.alteraforum.com/forum/attachment.php?attachmentid=6906
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    This RTL view bug is intermittent - I can see the inversion on your picture. But if you set RTL viewer options to uncheck "Group all related nodes", then inversion disappears. And when you check "Group all related nodes" again, then .... you will get the schematics view without inversion. So, this is some bug in RTL visualisation.

    I have a related question - is there some way to get the RTL view in an ASCII form, i.e. just the netlist? The way Quartus draws schematics is far from perfect and I would rather move elements manually using some other schematic entry tool.