incorrect variables synthesis or expected behavior for simple adder function

This is what I got from the Windows version

library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
    port 
    (
        a,b  : in std_logic_vector(3 downto 0);
        c,d    : out std_logic_vector(3 downto 0)
    );
end entity;
architecture rtl of toplevel is
   function plus_s_s (a,b : std_logic_vector) return std_logic_vector is
        variable s: std_logic_vector(a'range);
        variable carry: std_logic;
    begin
        carry := '0';
        for i in a'low to a'high loop
            s(i) := (a(i) xor b(i)) xor carry;
            carry := ((a(i) or b(i)) and carry ) or (a(i) and b(i));
        end loop;
        
        return s;
    end;
    
Constant ONE : std_logic_vector(3 downto 0) := b"0001" ;
begin
    
    --c <= plus_s_s(a,B"0001");
    c <= plus_s_s(a,ONE);
    d <= plus_s_s(a,b);
    
end rtl;