New ContributorIn old Quartus 9.1, I was able to overwrite input vwf file with simulation output (timing and functional). Also, I was able to see internal state of FSM machines in design (not connected to output pins). How can I do the same in Quartus Prime 18.1?
In Quartus Prime 18.1, even though I add the state machine (in the example that follows, is called "actual") in input Waveform.vwf, the simulation output does not show any value change in the state of the FSM. Here is the code of a sequence detector (1,1,0,1) implemented as Mealy:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pregunta1a is
port(clock: in std_logic;
data: in std_logic;
salida: out std_logic
);
end pregunta1a;
architecture mealy of pregunta1a is
type estado is (A,B,C,D,E);
signal actual: estado :=A;
signal futuro: estado;
begin
process (clock)
begin
if (clock'event and clock='1') then
actual <= futuro;
end if;
end process;
process (actual, data)
begin
futuro <= actual; -- default future state value
salida <= '0'; -- default output value
if (actual= A) then
if (data = '1') then
futuro <= B;
end if;
end if;
if (actual= B) then
if (data = '0') then
futuro <= A;
else
futuro <= C;
end if;
end if;
if (actual= C) then
if (data = '0') then
futuro <= D;
else
futuro <= E;
end if;
end if;
if (actual= D) then
if (data = '0') then
futuro <= A;
else
futuro <= B;
salida <= '1';
end if;
end if;
if (actual= E) then
if (data = '0') then
futuro <= A;
end if;
end if;
end process;
end mealy;
