I'm using the Agilex 5 FPGA E-Series 065B Premium Development Kit.There isn't much documentation - so I decided to generate the design example and run the simulation in Questa. I generated and ran the "full simulation" design example (MIPI DSI-2 Rx+Tx Simulation) in Quartus 25.1.1. The simulation fails almost immediately the with error "axis_m does not accept back pressure." I'm not sure if we should try to force the "axi4s_vin_in_tready" to always high or if something else in the design should be changed. So, there doesn't seem to be documentation on how to implement MIPI DSI-2 and the functional simulation doesn't work. Ultimately, I'm looking for documentation or a functional simulation that shows how to implement MIPI DSI-2 on an Agilex 5 FPGA.

Hi,IF this is not extremely urgent for you, I suggest to wait till the official user guide out (it might define the correct configuration for simulation purpose)ETA will be before end of next month.Else, please provide me with your Htotal HBend lanes, pixel in parallelIF possible the IP settings as well We can help you to define the best IP configuration for the simulation purposeRegards,Wincent_Altera

Hi, We're using a Raspberry Pi compatible display that is 800x600 at 60Hz (SVGA), so the spec is as follows:htotal: 1056hbend (hsync_end): 968DSI lanes: 2Pixel format (“pixels in parallel”): RGB888 (24 bpp)Per-lane rate @ RGB888, 2-lane: ≈ 530 Mb/s per laneI'm not sure about any other IP settings. We are using the IP in TX mode only.thanks,Steve

Hi Steve,Can you please share me the .ip file ?If you not sure where to locate it, perhaps printscreen on all the parameter "ip" "video timing" will be very helpful for meRegards,Wincent_Altera

Here are my settings for the MIPI DSI-2 IP tabs. A couple of notes:* IP tab: without knowing better, I went with the defaults so I'm not sure if these need to be adjusted* Video Timing tab: these are for a standard SVGA display (800x600 @ 60 Hz).1. IPGeneral OptionsControl and Status Registers (CSR) = checkedCRC insertion = checkedECC insertion = checkedFixed Latency Mode = checkedBuffer Depth = 4096DPHY Interface OptionsNumber of lanes = 2PPI bus width per lane = 2 bytesVideo Streaming Interface OptionsPixels in Parallel = 2Maximum pixels per video line = 128AXI4 TDATA width: 48 bitsVideo Packing/Unpacking OptionsMIPI DSI2-Data Type = RBG_24bit2. Video Timing MIPI DSI-2 IP (800×600 @ 60 Hz)Video Timing ListVideo timing configuration values = ManualDimensionsHTOTAL = 1056VTOTAL = 628Blank TimingHB_END = hfront + hsync + hback = 40 + 128 + 88 = 256V1B_START = 0 (blanking begins at line 0)V1B_END = vfront + vsync + vback = 1 + 4 + 23 = 28Sync TimingHS_START = hfront = 40HS_END = hfront + hsync = 40 + 128 = 168V1S_VSTART = vfront = 1V1S_HSTART = 0 (vsync asserted from the start of each affected line)V1S_VEND = vfront + vsync = 1 + 4 = 5V1S_HEND = 0 (vsync spans the full line)

Hi @SteveS109 There is calculation need to be fullfill for the Htotal and Hbend under the "video timing" tabThis will be include in the later published user guide (ETA 2-4 weeks from now , subject to change)By referring to your .ip setting active length = 128pip = 2data types = RGB_24bitUnder the "video timing" tab - please try to modified the value of Htotal and Hbend ONLY intoHtotal = 1751Hbend = 1623Other parameter such as V1S_VSTART, V1S_HSTART , V1S_VEND ... etc , you may remain the default value.Then re-run the simulation again. let me know if you still seeing the any failure.Regards,Wincent_Altera

Implementing MIPI DSI-2 on an Agilex 5 device

36 Replies

Wincent_Altera
Regular Contributor
3 months ago
Hi,
IF this is not extremely urgent for you, I suggest to wait till the official user guide out (it might define the correct configuration for simulation purpose)
ETA will be before end of next month.

Else, please provide me with your
Htotal
HBend
lanes,
pixel in parallel
IF possible the IP settings as well
We can help you to define the best IP configuration for the simulation purpose
Regards,
Wincent_Altera
SteveS109
Occasional Contributor
3 months ago
Hi, We're using a Raspberry Pi compatible display that is 800x600 at 60Hz (SVGA), so the spec is as follows:
htotal: 1056
hbend (hsync_end): 968
DSI lanes: 2
Pixel format (“pixels in parallel”): RGB888 (24 bpp)
Per-lane rate @ RGB888, 2-lane: ≈ 530 Mb/s per lane
I'm not sure about any other IP settings. We are using the IP in TX mode only.
thanks,
Steve
- Wincent_Altera
  Regular Contributor
  3 months ago
  Hi Steve,
  
  Can you please share me the .ip file ?
  If you not sure where to locate it, perhaps printscreen on all the parameter "ip" "video timing" will be very helpful for me
  
  Regards,
  Wincent_Altera
  - SteveS109
    Occasional Contributor
    3 months ago
    Here are my settings for the MIPI DSI-2 IP tabs. A couple of notes:
    * IP tab: without knowing better, I went with the defaults so I'm not sure if these need to be adjusted
    * Video Timing tab: these are for a standard SVGA display (800x600 @ 60 Hz).
    1. IP
    General Options
    Control and Status Registers (CSR) = checked
    CRC insertion = checked
    ECC insertion = checked
    Fixed Latency Mode = checked
    Buffer Depth = 4096
    DPHY Interface Options
    Number of lanes = 2
    PPI bus width per lane = 2 bytes
    Video Streaming Interface Options
    Pixels in Parallel = 2
    Maximum pixels per video line = 128
    AXI4 TDATA width: 48 bits
    Video Packing/Unpacking Options
    MIPI DSI2-Data Type = RBG_24bit
    2. Video Timing MIPI DSI-2 IP (800×600 @ 60 Hz)
    Video Timing List
    Video timing configuration values = Manual
    Dimensions
    HTOTAL = 1056
    VTOTAL = 628
    Blank Timing
    HB_END = hfront + hsync + hback = 40 + 128 + 88 = 256
    V1B_START = 0 (blanking begins at line 0)
    V1B_END = vfront + vsync + vback = 1 + 4 + 23 = 28
    Sync Timing
    HS_START = hfront = 40
    HS_END = hfront + hsync = 40 + 128 = 168
    V1S_VSTART = vfront = 1
    V1S_HSTART = 0 (vsync asserted from the start of each affected line)
    V1S_VEND = vfront + vsync = 1 + 4 = 5
    V1S_HEND = 0 (vsync spans the full line)
SteveS109
Occasional Contributor
3 months ago
I updated the parameters on the Video Timing tab changing only to these values: Htotal = 1751 and Hbend = 1623
I re-ran the simulation and this time, I see a fatal "CRC value is wrong" error instead of the original back pressure issue.
# dsi2_ed_sim_tb.test_inst: STARTING TEST!
# dsi2_ed_sim_tb.test_inst: Running test with 10 frames
# dsi2_ed_sim_tb.test_inst: Using VVP Image Information Config: '{}
# dsi2_ed_sim_tb.test_inst: Line Packet Length = 384 Bytes;
# dsi2_ed_sim_tb.test_inst:
# dsi2_ed_sim_tb.test_inst.run_test: Loading Tasklist to execute!
# dsi2_ed_sim_tb.test_inst.run_test: Estimated Tasklist size: 3860
# dsi2_ed_sim_tb.test_inst.run_test: Finished loading Tasklist!
# dsi2_ed_sim_tb.test_inst.run_test: This Tasklist contains: 991 tasks to execute!
# dsi2_ed_sim_tb.test_inst.run_test:
# dsi2_ed_sim_tb.test_inst.axis_source: Sending VVP Image Information Packet: 67005f007f0240
# ** Fatal: CRC value is wrong
# Time: 179030 ns Started: 179023333333 fs Scope: dsi2_ed_sim_tb.dut.dsi2_tx.dsi2_tx.dsi2.mipi_dsi2_tx_inst.<protected>.<protected>.<protected> File: ../../../rtl/ip/dsi2_dphy_sys/dsi2_dphy_sys_dsi2_tx/intel_mipi_dsi2_core_100/sim/intelfpga/mipi_dsi2_tx_packetizer.sv Line: 130
# ** Note: $finish : ../../../rtl/ip/dsi2_dphy_sys/dsi2_dphy_sys_dsi2_tx/intel_mipi_dsi2_core_100/sim/intelfpga/mipi_dsi2_tx_packetizer.sv(130)
# Time: 179030 ns Iteration: 10 Protected: /dsi2_ed_sim_tb/dut/dsi2_tx/dsi2_tx/dsi2/mipi_dsi2_tx_inst/<protected>/<protected>/<protected>
SteveS109
Occasional Contributor
3 months ago
In view of the previous fatal "CRC value is wrong" error, for debug purposes I decided to uncheck "CRC insertion" on the IP tab. regenerate, and re-run to see what would happen.
Unlike previous sims, the Sending VVP Image Information Packet line is now followed by Received VVP Image Information Packet - but is immediately followed by another error.
# dsi2_ed_sim_tb.test_inst.axis_source: Sending VVP Image Information Packet: 67005f007f0240
# dsi2_ed_sim_tb.test_inst.axis_sink : Received VVP Image Information Packet: 67005f007f0240
# ** Error: <protected>.<protected>: Unsupported data_type 0x00 for this function
# Time: 240163333333 fs Scope: <protected>.<protected> File: ../../hdl/sv_packages/mipi_pkg.sv Line: 130
# dsi2_ed_sim_tb.test_inst.axis_sink : Received VVP start of a new field of video
# ** Error: 1dsi2_ed_sim_tb.test_inst.axis_sink : Byte Error: Received 1 [0x1] expected 0 [0x0]
# Time: 240846666666 fs Scope: dsi2_ed_sim_tb.test_inst.axis_sink.check_byte File: ../../hdl/axis_sink.sv Line: 78
# dsi2_ed_sim_tb.test_inst.axis_sink : Byte Error at position 0 of 2000001 [0x2000001]
# ** Fatal: dsi2_ed_sim_tb.test_inst.axis_sink : Byte Error!
# Time: 240846666666 fs Scope: dsi2_ed_sim_tb.test_inst.axis_sink.check_remaining_pkt_bytes File: ../../hdl/axis_sink.sv Line: 147
# ** Note: $finish : ../../hdl/axis_sink.sv(147)
# Time: 240846666666 fs Iteration: 7 Region: /dsi2_ed_sim_tb/test_inst/run_test
SteveS109
Occasional Contributor
3 months ago
Somehow the "Accept solution" button got mistakenly clicked. This issue is not solved yet. I blame the cat.
- Wincent_Altera
  Regular Contributor
  3 months ago
  Hi Steve,
  
  Is okay, I have my cat who always come to my working table as well
  
  Back to the topic, do you re-generate the design testbench after updating the parameter ?
  If not , i would suggest to create a brand new one , I suspect is the previous run error causing current design corruption.
  May I know which simulation tools and Quartus version that you are using ?
  
  Regards,
  Wincent_Altera
SteveS109
Occasional Contributor
3 months ago
Great cat picture!
I'm using Quartus 25.1.1 Prime Pro and the Questa FPGA (not starter edition) simulator that comes with it.
I've been re-generating an entirely new design example to a new directory after each change. See the screen shots of the MIPI IP tabs (below).
When the design example finishes building, I cd into the mentor directory:
cd ~/mipi_example/new/ed_sim/sim/mentor
launch vsim
vsim &
Once Questa starts, inside the main Questa window
source run_msim_setup.tcl
# dsi2_ed_sim_tb.test_inst: STARTING TEST!
# dsi2_ed_sim_tb.test_inst: Running test with 10 frames
# dsi2_ed_sim_tb.test_inst: Using VVP Image Information Config: '{}
# dsi2_ed_sim_tb.test_inst: Line Packet Length = 384 Bytes;
# dsi2_ed_sim_tb.test_inst:
# dsi2_ed_sim_tb.test_inst.run_test: Loading Tasklist to execute!
# dsi2_ed_sim_tb.test_inst.run_test: Estimated Tasklist size: 3860
# dsi2_ed_sim_tb.test_inst.run_test: Finished loading Tasklist!
# dsi2_ed_sim_tb.test_inst.run_test: This Tasklist contains: 991 tasks to execute!
# dsi2_ed_sim_tb.test_inst.run_test:
# dsi2_ed_sim_tb.test_inst.axis_source: Sending VVP Image Information Packet: 67005f007f0240
# dsi2_ed_sim_tb.test_inst.axis_sink : Received VVP Image Information Packet: 67005f007f0240
# ** Error: <protected>.<protected>: Unsupported data_type 0x00 for this function
# Time: 240163333333 fs Scope: <protected>.<protected> File: ../../hdl/sv_packages/mipi_pkg.sv Line: 130
# dsi2_ed_sim_tb.test_inst.axis_sink : Received VVP start of a new field of video
# ** Error: 1dsi2_ed_sim_tb.test_inst.axis_sink : Byte Error: Received 1 [0x1] expected 0 [0x0]
# Time: 240846666666 fs Scope: dsi2_ed_sim_tb.test_inst.axis_sink.check_byte File: ../../hdl/axis_sink.sv Line: 78
# dsi2_ed_sim_tb.test_inst.axis_sink : Byte Error at position 0 of 2000001 [0x2000001]
# ** Fatal: dsi2_ed_sim_tb.test_inst.axis_sink : Byte Error!
# Time: 240846666666 fs Scope: dsi2_ed_sim_tb.test_inst.axis_sink.check_remaining_pkt_bytes File: ../../hdl/axis_sink.sv Line: 147
# ** Note: $finish : ../../hdl/axis_sink.sv(147)
# Time: 240846666666 fs Iteration: 7 Region: /dsi2_ed_sim_tb/test_inst/run_test
# 1
# Break at ../../hdl/axis_sink.sv line 147
That's were it ends.
- Wincent_Altera
  Regular Contributor
  3 months ago
  Hi @SteveS109 ,
  
  let me try on my place, it may take sometime, get back to you later
  
  Regards,
  Wincent
  - Wincent_Altera
    Regular Contributor
    3 months ago
    Hi @SteveS109 ,
    
    I check back your step, i think there is something not correct.
    vsim & - open the GUI
    do msim_setup.tcl
    ld_debug - then add wave
    run -all
    I try that in my simulation environment - It run well
    
    Can you please check back ?
    
    Regards,
    Wincent_Altera
SteveS109
Occasional Contributor
3 months ago
vsim &
do msim_setup.tcl
ld_debug
view -new wave
add wave -position insertpoint sim:/dsi2_ed_sim_tb/dut/*
run -all
I really wanted to see what was happening at the DUT - which looks pretty good.
I still see the same simulation failure - but yours is clean???
Error: unsupported data type 0x00
Error: byte Error
Fatal: Byte Error!
- Wincent_Altera
  Regular Contributor
  3 months ago
  Hi @SteveS109 ,
  
  I will zip my file and sent to you. please try that out.
  
  Regards,
  Wincent
  - SteveS109
    Occasional Contributor
    3 months ago
    I was looking for your link to a zip file but did not see it. Have you sent it?
SteveS109
Occasional Contributor
3 months ago
In case I missed something or made a mistake, I've regenerated fresh design examples in a new directories a few times (mipi dsi22 rx+tx simulation, full simulation, CRC insertion on IP tab=unchecked) and I get the same simulation result as my previous post. I'm not sure how you are getting a clean simulation.
SteveS109
Occasional Contributor
3 months ago
Hi Wincent - I see that this issue was successfully migrated from the Intel community forum site to the new Altera site.
The simulation of the MIPI DSI-2 IP design example generated from Quartus 25.3 looks much better. I didn't see any documention in Q25.3 on how to correctly calculate the video timing parameters.
I presented the following prompt to chatCPT:
"Generate and show the calculations for the MIPI DSI-2 video timing parameters for an 800x600 SVGA MIPI display. The calculated parameters should include HTOTAL, VTOTAL, HB_END, V1B_START, V1B_END, HS_START, HS_END, V1S_VSTART, V1S_HSTART, V1S_VEND, and V1S_HEND"
The response was:
When I plug these values into the Video Timing tab for MIPI DSI-2 IP, there are 4 errors:
I'm not a MIPI display expert - but it seems that there are equation differences between what you are using and what others (e.g., chatGPT) understand the equations should be.
Could you please provide complete details on how to calculate the Video Timing IP parameters. Please use the SVGA display as an example if you wish.
SteveS109
Occasional Contributor
3 months ago
FYI - the link to the user guide under the Platform Designer IP "Details" tab is broken:
User Guide https://www.intel.com/content/www/us/en/docs/programmable/860639.html