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SteveS109
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3 months ago

Implementing MIPI DSI-2 on an Agilex 5 device

I'm using the Agilex 5 FPGA E-Series 065B Premium Development Kit. There isn't much documentation - so I decided to generate the design example and run the simulation in Questa. I generated and ran ...
SteveS109's avatar
SteveS109
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Hi Wincent - I see that this issue was successfully migrated from the Intel community forum site to the new Altera site.

The simulation of the MIPI DSI-2 IP design example generated from Quartus 25.3 looks much better.  I didn't see any documention in Q25.3 on how to correctly calculate the video timing parameters.

I presented the following prompt to chatCPT:

"Generate and show the calculations for the MIPI DSI-2 video timing parameters for an 800x600 SVGA MIPI display. The calculated parameters should include HTOTAL, VTOTAL, HB_END, V1B_START, V1B_END, HS_START, HS_END, V1S_VSTART, V1S_HSTART, V1S_VEND, and V1S_HEND"

The response was:

When I plug these values into the Video Timing tab for MIPI DSI-2 IP, there are 4 errors:

I'm not a MIPI display expert - but it seems that there are equation differences between what you are using and what others (e.g., chatGPT) understand the equations should be.

Could you please provide complete details on how to calculate the Video Timing IP parameters.  Please use the SVGA display as an example if you wish.