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SteveS109's avatar
SteveS109
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Implementing MIPI DSI-2 on an Agilex 5 device

I'm using the Agilex 5 FPGA E-Series 065B Premium Development Kit. There isn't much documentation - so I decided to generate the design example and run the simulation in Questa. I generated and ran ...
SteveS109's avatar
SteveS109
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Hi, We're using a Raspberry Pi compatible display that is 800x600 at 60Hz (SVGA), so the spec is as follows:

htotal: 1056

hbend (hsync_end): 968

DSI lanes: 2

Pixel format (“pixels in parallel”): RGB888 (24 bpp)

Per-lane rate @ RGB888, 2-lane: ≈ 530 Mb/s per lane

I'm not sure about any other IP settings. We are using the IP in TX mode only.

thanks,

Steve

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
5 months ago

Hi Steve,

Can you please share me the .ip file ?
If you not sure where to locate it, perhaps printscreen on all the parameter "ip" "video timing" will be very helpful for me


Regards,
Wincent_Altera