SteveS109
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Re: Implementing MIPI DSI-2 on an Agilex 5 device
The top-level Verilog module ports for the IP are as follows: I think guidance on how to generate a blackbox IP component for this is what is needed along with top-level connections including what needs to be exported. // dsi2_dphy_sys.v // Generated using ACDS version 25.3 109 `timescale 1 ps / 1 ps module dsi2_dphy_sys ( input wire dsi2_tx_control_write, // dsi2_tx_control.write input wire dsi2_tx_control_read, // .read input wire [8:0] dsi2_tx_control_address, // .address input wire [31:0] dsi2_tx_control_writedata, // .writedata output wire [31:0] dsi2_tx_control_readdata, // .readdata output wire dsi2_tx_control_readdatavalid, // .readdatavalid output wire dsi2_tx_control_waitrequest, // .waitrequest input wire [3:0] dsi2_tx_control_byteenable, // .byteenable input wire [47:0] dsi2_tx_axi4s_vid_in_tdata, // dsi2_tx_axi4s_vid_in.tdata input wire dsi2_tx_axi4s_vid_in_tvalid, // .tvalid output wire dsi2_tx_axi4s_vid_in_tready, // .tready input wire dsi2_tx_axi4s_vid_in_tlast, // .tlast input wire [5:0] dsi2_tx_axi4s_vid_in_tuser, // .tuser input wire dsi2_tx_frame_start_conduit, // dsi2_tx_frame_start.conduit output wire dsi2_tx_axi4s_clk_bridge_out_clk_clk, // dsi2_tx_axi4s_clk_bridge_out_clk.clk output wire dsi2_tx_axi4s_reset_bridge_out_reset_reset, // dsi2_tx_axi4s_reset_bridge_out_reset.reset input wire mipi_dphy_rzq_rzq, // mipi_dphy_rzq.rzq input wire mipi_dphy_ref_clk_0_clk, // mipi_dphy_ref_clk_0.clk input wire [11:0] mipi_dphy_axi_lite_awaddr, // mipi_dphy_axi_lite.awaddr input wire mipi_dphy_axi_lite_awvalid, // .awvalid output wire mipi_dphy_axi_lite_awready, // .awready input wire [31:0] mipi_dphy_axi_lite_wdata, // .wdata input wire [3:0] mipi_dphy_axi_lite_wstrb, // .wstrb input wire mipi_dphy_axi_lite_wvalid, // .wvalid output wire mipi_dphy_axi_lite_wready, // .wready output wire [1:0] mipi_dphy_axi_lite_bresp, // .bresp output wire mipi_dphy_axi_lite_bvalid, // .bvalid input wire mipi_dphy_axi_lite_bready, // .bready input wire [11:0] mipi_dphy_axi_lite_araddr, // .araddr input wire mipi_dphy_axi_lite_arvalid, // .arvalid output wire mipi_dphy_axi_lite_arready, // .arready output wire [31:0] mipi_dphy_axi_lite_rdata, // .rdata output wire [1:0] mipi_dphy_axi_lite_rresp, // .rresp output wire mipi_dphy_axi_lite_rvalid, // .rvalid input wire mipi_dphy_axi_lite_rready, // .rready input wire [2:0] mipi_dphy_axi_lite_arprot, // .arprot input wire [2:0] mipi_dphy_axi_lite_awprot, // .awprot output wire mipi_dphy_reg_bus_reg_wr_en_o, // mipi_dphy_reg_bus.reg_wr_en_o output wire mipi_dphy_reg_bus_reg_rd_en_o, // .reg_rd_en_o output wire [10:0] mipi_dphy_reg_bus_reg_raddr_o, // .reg_raddr_o output wire [10:0] mipi_dphy_reg_bus_reg_waddr_o, // .reg_waddr_o output wire [3:0] mipi_dphy_reg_bus_reg_be_o, // .reg_be_o output wire [31:0] mipi_dphy_reg_bus_reg_din_o, // .reg_din_o input wire [31:0] mipi_dphy_reg_bus_reg_dout_i, // .reg_dout_i output wire mipi_dphy_LINK1_link_core_srst_reset_n, // mipi_dphy_LINK1_link_core_srst.reset_n output wire [1:0] mipi_dphy_LINK1_dphy_io_dphy_link_dp, // mipi_dphy_LINK1_dphy_io.dphy_link_dp output wire [1:0] mipi_dphy_LINK1_dphy_io_dphy_link_dn, // .dphy_link_dn output wire mipi_dphy_LINK1_dphy_io_dphy_link_cp, // .dphy_link_cp output wire mipi_dphy_LINK1_dphy_io_dphy_link_cn, // .dphy_link_cn output wire mipi_dphy_link1_link_core_clock_bridge_out_clk_clk, // mipi_dphy_link1_link_core_clock_bridge_out_clk.clk output wire mipi_dphy_link1_link_core_reset_bridge_out_reset_reset // mipi_dphy_link1_link_core_reset_bridge_out_reset.reset );Re: Implementing MIPI DSI-2 on an Agilex 5 device
Thank you - we look forward to receiving KDB information and patch. In the meantime, it would help to have a blackbox IP component that could just be instantiated with Platform Designer as a placeholder. Is that something that you can easily supply or provide guidance on how to generate? We only need the MIPI DSI2 TX.Re: Implementing MIPI DSI-2 on an Agilex 5 device
The simulation with default video timing looked great to me - it looks very solid. No issue with the simulation - it looks much better in the design example from Quartus 25.3. It is a very long sim so I didn't run to completion - I stopped it after about 1/2 hour but it looks very good. My remaining concern is about generating video timing IP parameters for an 800x600 display. If you have any informal equations to copy & paste into the forum - that would be great. As I mentioned, the params generated by chatGPT were not acceptable to Quartus 25.3 when attempting to generate the IP design example. You didn't explicitly say that the parameters in your screen shots above will work for an SVGA display - but I can try it. I will use what you provided to proceed through the whole build process.Re: Implementing MIPI DSI-2 on an Agilex 5 device
Hi Wincent - I see that this issue was successfully migrated from the Intel community forum site to the new Altera site. The simulation of the MIPI DSI-2 IP design example generated from Quartus 25.3 looks much better. I didn't see any documention in Q25.3 on how to correctly calculate the video timing parameters. I presented the following prompt to chatCPT: "Generate and show the calculations for the MIPI DSI-2 video timing parameters for an 800x600 SVGA MIPI display. The calculated parameters should include HTOTAL, VTOTAL, HB_END, V1B_START, V1B_END, HS_START, HS_END, V1S_VSTART, V1S_HSTART, V1S_VEND, and V1S_HEND" The response was: When I plug these values into the Video Timing tab for MIPI DSI-2 IP, there are 4 errors: I'm not a MIPI display expert - but it seems that there are equation differences between what you are using and what others (e.g., chatGPT) understand the equations should be. Could you please provide complete details on how to calculate the Video Timing IP parameters. Please use the SVGA display as an example if you wish.
