Occasional Contributor
Hi SteveS109 ,
Please refer to my .ip setting below. I try it and it is success.
Please ensure that you had run the "Analysis & Synthesis" before running the simulation
Locate your directory under ../x/../ed_sim/sim/mentor
I can get my simulation PASS
Let me know if you still unable to do it.
Regards,
Wincent
Occasional ContributorThe simulation with default video timing looked great to me - it looks very solid. No issue with the simulation - it looks much better in the design example from Quartus 25.3. It is a very long sim so I didn't run to completion - I stopped it after about 1/2 hour but it looks very good.
My remaining concern is about generating video timing IP parameters for an 800x600 display. If you have any informal equations to copy & paste into the forum - that would be great. As I mentioned, the params generated by chatGPT were not acceptable to Quartus 25.3 when attempting to generate the IP design example.
You didn't explicitly say that the parameters in your screen shots above will work for an SVGA display - but I can try it. I will use what you provided to proceed through the whole build process.
Occasional ContributorFYI/for what it's worth - simulating the MIPI DSI-2 design example from Q25.3 also passed for me.
Hi SteveS109 ,
Glad that it work.
FYI for v25.1.1 there will be no warning for any calculation error for the Htotal and Hbend.
While in 25.3 onwards, once the value is not fit, there will be an error or warning message come out.
To fix this, I will file and KDB and internally we are preparing a patch (to tune the default value of Example design into working value - Subject to change).
Let me know if there is anything else I can help you out, please accept my apology for the delay of support due to forum migration, thanks for reaching me back. Wish you have a great day with your cat
Regards,
Wincent_Altera
Occasional ContributorThank you - we look forward to receiving KDB information and patch.
In the meantime, it would help to have a blackbox IP component that could just be instantiated with Platform Designer as a placeholder. Is that something that you can easily supply or provide guidance on how to generate? We only need the MIPI DSI2 TX.
Hi SteveS109 ,
The parameter that I provided to you was for 2k resolution.
For 800x600 I would need to re-calculate and test it again, come back to you later.
Regards,
Wincent
Occasional ContributorThat would be great - thank you.
Regular ContributorFirst
I tested the following configuration for 800x96 only, and it passed the simulation successfully.
It is configured as close as possible for simulation purposes.
Due to a limitation I discovered — the frame height in the simulation is fixed at 96 — it effectively simulates a resolution of 800x96.
The only change you’ll need to make for your final hardware system is to change `C_TIM_VTOTAL` to `630` to update the active height to `600`.
(Note: this change will not pass simulation due to the limitation in the simulation components.)
You may follow the `.ip` settings below to try it out.
For the simulation variant, you can select either *fast sim* or *full sim*, depending on your needs.
Second
Regarding the black-box IP component:
You can have the IP itself, but when you generate the IP, Platform Designer will automatically create a black-box Verilog file.
For example, you can:
1. Select the **DSI-2 IP** from the IP Catalog in Quartus.
2. Name the new IP `dsi_example.ip`.
3. Configure the IP as required.
4. Generate the IP (not the example design).
5. Look in the new `dsi_example` folder under the Quartus project folder and find `dsi_example_bb.v`, which is an empty Verilog component with the correct I/O for the selected configuration.
Regards,
Wincent
